公开(公告)号：US11249384B2

公开(公告)日：2022-02-15

申请号：US16441700

申请日：2019-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Cheng Hsu ,  Chi-Ping Wen ,  Tzu Yi Wang ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/22

Abstract: A method of manufacturing an extreme ultraviolet (EUV) lithography mask includes forming an image pattern in an absorption layer of EUV mask blank. The EUV mask blank includes: a multilayer stack including alternating molybdenum (Mo) and silicon (Si) layers disposed over a first surface of a mask substrate, a capping layer disposed over the multilayer stack, and an absorption layer disposed over the capping layer. A border region surrounds the image pattern having a trench wherein the absorption layer, the capping layer and at least a portion of the multilayer stack are etched. Concave sidewalls are formed in the border region or an inter-diffused portion is formed in the multilayer stack of the trench.

公开(公告)号：US11221554B2

公开(公告)日：2022-01-11

申请号：US16746640

申请日：2020-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/22

Abstract: An extreme ultra-violet (EUV) mask and method for fabricating the same is disclosed. For example, the EUV mask includes a substrate, a multi-layered mirror layer formed on the substrate, a metal capping layer formed on the multi-layered mirror layer, and a multi-layered absorber layer formed on the metal capping layer. The multi-layered absorber layer includes features etched into the multi-layered absorber layer to define structures on a semiconductor device.

公开(公告)号：US11143954B2

公开(公告)日：2021-10-12

申请号：US16018444

申请日：2018-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chang Hsueh ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/70 ,  G03F1/38 ,  G03F1/54 ,  G03F1/24 ,  G03F1/36

Abstract: Photomasks and methods of fabricating the photomasks are provided herein. In some examples, a layout for forming an integrated circuit device is received. The layout includes a set of printing features. A region of the layout is identified. The region is at a distance from the set of printing features such that an exposure region associated with a feature in the region does not affect a set of exposure regions associated with the set of printing features. A plurality of non-printing features is inserted into the region. A photomask is fabricated based on the layout.

公开(公告)号：US20210311383A1

公开(公告)日：2021-10-07

申请号：US17350685

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Yih-Chen Su ,  Chi-Kuang Tsai ,  Ta-Cheng Lien ,  Tzu Yi Wang ,  Jong-Yuh Chang ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/26 ,  G03F7/20 ,  H01L21/263 ,  G03F1/80 ,  G03F1/84

Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.

公开(公告)号：US20190391480A1

公开(公告)日：2019-12-26

申请号：US16018444

申请日：2018-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chang Hsueh ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/20 ,  G03F1/38 ,  G03F1/78 ,  G03F1/24 ,  G03F1/54 ,  G03F7/20 ,  H01L21/033

Abstract: Photomasks and methods of fabricating the photomasks are provided herein. In some examples, a layout for forming an integrated circuit device is received. The layout includes a set of printing features. A region of the layout is identified. The region is at a distance from the set of printing features such that an exposure region associated with a feature in the region does not affect a set of exposure regions associated with the set of printing features. A plurality of non-printing features is inserted into the region. A photomask is fabricated based on the layout.

公开(公告)号：US12181797B2

公开(公告)日：2024-12-31

申请号：US17483302

申请日：2021-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Ping-Hsun Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F7/004 ,  H01L21/033

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a multi-layer patterned absorber layer on the reflective multilayer stack is provided. Disclosed embodiments include an absorber layer that includes an alloy comprising ruthenium (Ru), chromium (Cr), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), tungsten (W) or palladium (Pd), and at least one alloying element. The at least one alloying element includes ruthenium (Ru), chromium (Cr), tantalum (Ta), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), hafnium (Hf), boron (B), nitrogen (N), silicon (Si), zirconium (Zr) or vanadium (V). Other embodiments include a multi-layer patterned absorber structure with layers that include an alloy and an alloying element, where at least two of the layers of the multi-layer structure have different compositions.

公开(公告)号：US12153339B2

公开(公告)日：2024-11-26

申请号：US17390603

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/64 ,  B82Y30/00 ,  B82Y40/00 ,  G03F1/82 ,  G03F7/00 ,  H01L21/033

Abstract: A pellicle for protecting a photomask from contaminant particles is provided. The pellicle includes a pellicle membrane containing at least one porous film. The at least one porous film includes a network of a plurality of nanotubes. At least one nanotube of the plurality of nanotubes includes a core nanotube and a shell nanotube surrounding the core nanotube. The core nanotube includes a material different from the shell nanotube. The pellicle further includes a pellicle border attached to the pellicle membrane along a peripheral region of the pellicle membrane and a pellicle frame attached to the pellicle border.

公开(公告)号：US11829062B2

公开(公告)日：2023-11-28

申请号：US17065712

申请日：2020-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  H01L21/033 ,  H01L21/027 ,  G03F1/54

CPC classification number: G03F1/24 ,  G03F1/54 ,  H01L21/0274 ,  H01L21/0332

Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.

公开(公告)号：US11650493B2

公开(公告)日：2023-05-16

申请号：US17568037

申请日：2022-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Chun-Fu Yang ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/70 ,  G03F7/2004

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

公开(公告)号：US11531262B2

公开(公告)日：2022-12-20

申请号：US17083348

申请日：2020-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Ta-Cheng Lien ,  Wen-Chang Hsueh

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/48

Abstract: A reflective mask blank includes a substrate, a reflective multilayer (RML) disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer has length or width dimensions smaller than the capping layer, and part of the capping layer is exposed by the absorber layer. The dimension of the absorber layer and the hard mask layer ranges between 146 cm to 148 cm. The dimensions of the substrate, the RML, and the capping layer range between 150 cm to 152 cm.