公开(公告)号：US20230387265A1

公开(公告)日：2023-11-30

申请号：US18366297

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/0847 ,  H01L29/785 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/42356 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/66545 ,  H01L21/823864 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823431 ,  H01L2029/7858

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US11605562B2

公开(公告)日：2023-03-14

申请号：US17141126

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Tzu-Chung Wang ,  Kai-Tai Chang ,  Wei-Sheng Yun

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/04 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.

公开(公告)号：US11387360B2

公开(公告)日：2022-07-12

申请号：US16874526

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US11038034B2

公开(公告)日：2021-06-15

申请号：US16394152

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/22 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US10930498B2

公开(公告)日：2021-02-23

申请号：US16598275

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/8234

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US20200343302A1

公开(公告)日：2020-10-29

申请号：US16394152

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC: H01L27/24 ,  H01L27/22 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US20200127138A1

公开(公告)日：2020-04-23

申请号：US16255334

申请日：2019-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Chia-Cheng Ho ,  Tzu-Chung Wang ,  Tung Ying Lee ,  Jin Cai ,  Ming-Shiang Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US12224334B2

公开(公告)日：2025-02-11

申请号：US18324636

申请日：2023-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Tung-Ying Lee ,  Tse-An Chen ,  Tzu-Chung Wang ,  Miin-Jang Chen ,  Yu-Tung Yin ,  Meng-Chien Yang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

公开(公告)号：US11444174B2

公开(公告)日：2022-09-13

申请号：US16562416

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/10 ,  H01L29/423 ,  H01L21/308

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

公开(公告)号：US10886180B2

公开(公告)日：2021-01-05

申请号：US16426428

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Tzu-Chung Wang ,  Kai-Tai Chang ,  Wei-Sheng Yun

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.