公开(公告)号：US09564448B2

公开(公告)日：2017-02-07

申请号：US14718171

申请日：2015-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L21/283 ,  H01L27/115 ,  H01L29/78 ,  H01L21/28 ,  H01L29/34 ,  H01L29/423 ,  H01L29/66 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76805 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/34 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底和形成在衬底上的控制栅极。 半导体器件结构还包括形成在衬底上的存储器栅极和形成在存储器栅极的侧壁上的第一间隔物。 半导体器件结构还包括形成在存储器栅极上的触点，其中触点的一部分延伸到第一间隔物中。

公开(公告)号：US09196825B2

公开(公告)日：2015-11-24

申请号：US14016343

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/66 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract translation: 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括被钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。

公开(公告)号：US20200083441A1

公开(公告)日：2020-03-12

申请号：US16683568

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

公开(公告)号：US20170194559A1

公开(公告)日：2017-07-06

申请号：US15463500

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L43/08

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

公开(公告)号：US09614145B2

公开(公告)日：2017-04-04

申请号：US14918671

申请日：2015-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

公开(公告)号：US09397228B2

公开(公告)日：2016-07-19

申请号：US14560353

申请日：2014-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chang-Ming Wu ,  Wei-Hang Huang ,  Shih-Chang Liu

IPC: H01L21/3205 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L29/66825 ,  H01L27/11531 ,  H01L29/42328

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括半导体衬底上的第一栅极堆叠。 半导体器件结构包括半导体衬底上的第二栅极堆叠。 半导体器件结构包括在第一栅极堆叠和第二栅极堆叠之间的擦除栅极。 擦除栅极具有朝向半导体衬底凹陷的凹陷。 半导体器件结构包括与第一栅极堆叠相邻的第一字线。 半导体器件结构包括与第二栅极堆叠相邻的第二字线。

公开(公告)号：US20150061052A1

公开(公告)日：2015-03-05

申请号：US14016343

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract translation: 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。