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公开(公告)号：US11342379B2
公开(公告)日：2022-05-24
申请号：US16408898
申请日：2019-05-10
发明人： Fu-Ting Sung , Chung-Chiang Min , Yuan-Tai Tseng
摘要： Some embodiments relate to a memory device. The memory device includes a top electrode overlying a bottom electrode. A data storage layer overlies the bottom electrode. The bottom electrode cups an underside of the data storage layer. The top electrode overlies the data storage layer. A top surface of the bottom electrode is aligned with a top surface of the top electrode.
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公开(公告)号：US11258007B2
公开(公告)日：2022-02-22
申请号：US17065606
申请日：2020-10-08
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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公开(公告)号：US10510952B2
公开(公告)日：2019-12-17
申请号：US15783030
申请日：2017-10-13
发明人： Fu-Ting Sung , Chern-Yow Hsu , Shih-Chang Liu
IPC分类号： H01L45/00 , H01L43/12 , H01L21/311
摘要： A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.
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公开(公告)号：US20160043306A1
公开(公告)日：2016-02-11
申请号：US14918671
申请日：2015-10-21
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
摘要翻译： 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。
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公开(公告)号：US09209392B1
公开(公告)日：2015-12-08
申请号：US14513781
申请日：2014-10-14
发明人： Fu-Ting Sung , Chern-Yow Hsu , Shih-Chang Liu
CPC分类号： H01L45/1233 , H01L45/08 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.
摘要翻译： 本公开涉及具有提供RRAM单元的有效切换的底部电极的电阻随机存取存储器（RRAM）单元以及相关联的形成方法。 在一些实施例中，RRAM单元具有由间隔物和底部电介质层包围的底部电极。 底部电极，间隔物和底部电介质层设置在由下部电介质层（ILD）层围绕的下部金属互连层上。 具有可变电阻的电介质数据存储层位于底部电介质层和底部电极之上，并且顶部电极设置在电介质数据存储层上。 间隔物的放置使后面形成的底部电极变窄，从而提高RRAM电池的开关效率。
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公开(公告)号：US09048316B2
公开(公告)日：2015-06-02
申请号：US14013653
申请日：2013-08-29
IPC分类号： H01L27/115 , G11C16/16 , H01L29/78 , H01L21/28
CPC分类号： H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.
摘要翻译： 提供半导体器件结构的机构的实施例。 半导体器件结构包括衬底和设置在衬底上的字线单元。 半导体器件还包括设置在衬底上并与字线单元相邻并且在存储器栅极的侧壁上的间隔物的存储器栅极。 间隔物和字线单元位于存储器栅极的相对侧。 此外，存储器栅极的顶表面和存储器栅极的侧壁之间的角度在约75°至约90°的范围内。
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公开(公告)号：US11050021B2
公开(公告)日：2021-06-29
申请号：US16678538
申请日：2019-11-08
发明人： Chern-Yow Hsu , Fu-Ting Sung , Shih-Chang Liu
摘要： A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a dielectric layer over the bottom electrode layer. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the dielectric layer and patterning the bottom electrode layer, the dielectric layer, and the top electrode layer to form a dielectric structure between a bottom electrode and a top electrode. The method for manufacturing a semiconductor structure further includes etching the bottom electrode from a sidewall of the bottom electrode to partially expose a bottom surface of the dielectric structure.
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公开(公告)号：US20210043832A1
公开(公告)日：2021-02-11
申请号：US17065606
申请日：2020-10-08
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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公开(公告)号：US10825825B2
公开(公告)日：2020-11-03
申请号：US16510043
申请日：2019-07-12
IPC分类号： H01L27/11568 , H01L29/78 , H01L21/28 , H01L29/34 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/11521 , H01L23/528 , H01L29/49 , H01L21/768
摘要： Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.
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公开(公告)号：US10529916B2
公开(公告)日：2020-01-07
申请号：US15463500
申请日：2017-03-20
摘要： An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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