公开(公告)号：US20240363366A1

公开(公告)日：2024-10-31

申请号：US18771181

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US11569562B2

公开(公告)日：2023-01-31

申请号：US16997958

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ping Wang ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Chung-Yi Hsu

IPC: H01Q1/22 ,  H01Q9/04 ,  H01L23/31 ,  H01L23/66

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

公开(公告)号：US20220262765A1

公开(公告)日：2022-08-18

申请号：US17739458

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Jung Yang ,  Yen-Ping Wang

IPC: H01L23/00

Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

公开(公告)号：US20200343203A1

公开(公告)日：2020-10-29

申请号：US16924116

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

公开(公告)号：US20190244834A1

公开(公告)日：2019-08-08

申请号：US16389993

申请日：2019-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L21/768 ,  H01L23/31

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.

公开(公告)号：US20190123017A1

公开(公告)日：2019-04-25

申请号：US16223274

申请日：2018-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC: H01L23/00

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

公开(公告)号：US20190067039A1

公开(公告)日：2019-02-28

申请号：US15690300

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.

公开(公告)号：US10163854B2

公开(公告)日：2018-12-25

申请号：US15803673

申请日：2017-11-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuei-Tang Wang ,  Kai-Chiang Wu ,  Chieh-Yen Chen ,  Yen-Ping Wang ,  Shou-Zen Chang

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/03 ,  H01L23/31

Abstract: A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material.

公开(公告)号：US12080563B2

公开(公告)日：2024-09-03

申请号：US17994841

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20240055371A1

公开(公告)日：2024-02-15

申请号：US18151556

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Kuo-Chiang Ting ,  Yu-Hsiung Wang ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Cheng-Wei Huang ,  Yen-Ping Wang ,  Chang-Wen Huang ,  Sheng-Ta Lin ,  Li-Cheng Hu ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/3178 ,  H01L21/565

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.