公开(公告)号：US20200058508A1

公开(公告)日：2020-02-20

申请号：US16210641

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni YU ,  Zhi-Chang LIN ,  Wei-Hao WU ,  Huan-Chieh SU ,  Chung-Wei HSU ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A method for forming a FinFET device structure is provided. The method for foiming a FinFET device structure includes forming a fin structure and a fin isolation structure over a substrate, and forming a metal stack over the fin structure and the fin isolation structure. The method for forming a FinFET device structure also includes partially removing the metal stack so that a top surface of the fin isolation structure is exposed, and forming a dielectric material over the metal stack and covering the top surface of the fin isolation structure. The method for forming a FinFET device structure further includes patterning the dielectric material and the metal stack to form a metal gate structure and an insulating structure over the metal gate structure.

公开(公告)号：US20200020794A1

公开(公告)日：2020-01-16

申请号：US16033256

申请日：2018-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Kai-Chieh YANG ,  Chia-Wei SU ,  Jia-Ni YU ,  Wei-Hao WU ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/302 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

公开(公告)号：US20190088762A1

公开(公告)日：2019-03-21

申请号：US15706456

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh SU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Jia-Ni YU ,  Wei-Hao WU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a gate trench; filling a recess in the gate electrode layer with a dielectric feature; and etching back the gate electrode layer from top end surfaces of the gate electrode layer while leaving a portion of the gate electrode layer under the dielectric feature.

公开(公告)号：US20250098222A1

公开(公告)日：2025-03-20

申请号：US18961193

申请日：2024-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Jin CAI ,  Zhi-Chang LIN ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L21/22 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

公开(公告)号：US20240194758A1

公开(公告)日：2024-06-13

申请号：US18584862

申请日：2024-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Kuan-Ting PAN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/78696

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US20230065208A1

公开(公告)日：2023-03-02

申请号：US17463365

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han CHUANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.

公开(公告)号：US20220336220A1

公开(公告)日：2022-10-20

申请号：US17809847

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu WANG ,  Zhi-Chang LIN ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

公开(公告)号：US20220246768A1

公开(公告)日：2022-08-04

申请号：US17723283

申请日：2022-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. The bottom isolation layer has a seam therein, and the seam exposes a sidewall of the bottom spacer.

公开(公告)号：US20220093512A1

公开(公告)日：2022-03-24

申请号：US17027344

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lo-Heng CHANG ,  Kuo-Cheng CHIANG ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Shih-Cheng CHEN ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.

公开(公告)号：US20220037506A1

公开(公告)日：2022-02-03

申请号：US16947381

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng CHEN ,  Kuo-Cheng CHIANG ,  Zhi-Chang LIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.