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    EMBEDDED MEMORY DEVICE WITH REDUCED PLASMA-INDUCED DAMAGE AND METHODS OF FORMING THE SAME
    13.
    发明公开
    EMBEDDED MEMORY DEVICE WITH REDUCED PLASMA-INDUCED DAMAGE AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240113043A1

    公开(公告)日：2024-04-04

    申请号：US18303631

    申请日：2023-04-20

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Wen-Chun You

    IPC: H01L23/60 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00

    CPC classification number: H01L23/60 ,  H10B53/30 ,  H10B61/00 ,  H10B63/80

    Abstract: A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.

    SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
    17.
    发明申请
    SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF 有权
    半导体布置及其形成

    公开(公告)号：US20150162329A1

    公开(公告)日：2015-06-11

    申请号：US14097516

    申请日：2013-12-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

    Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ming Chyi Liu

    IPC: H01L27/088 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

    CPC classification number: H01L27/088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/11521 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

    Abstract translation: 对半导体装置及其形成方法进行说明。 半导体装置包括在有源区的第一侧上的第一栅极结构和在有源区的第二侧上的第二栅极结构，其中第一栅极结构和第二栅极结构共享有源区。 形成半导体检测的方法包括在形成第一栅极结构之前形成有源区的深度注入，然后形成有源区的浅植入物。 在形成第一栅极结构之前形成深度注入减轻了对第一栅极结构劣化的蚀刻工艺的需要。 因此，第一栅极结构具有期望的构造，并且能够形成为更接近其它栅极结构以增强器件密度。

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