公开(公告)号：US11152262B2

公开(公告)日：2021-10-19

申请号：US16680755

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yi Lee ,  Ting-Gang Chen ,  Chieh-Ping Wang ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/02

Abstract: A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

公开(公告)号：US10276677B2

公开(公告)日：2019-04-30

申请号：US15494023

申请日：2017-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Yun-Wen Chu ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Shin-Yeu Tsai ,  Shih-Chieh Chang

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.

公开(公告)号：US20150048475A1

公开(公告)日：2015-02-19

申请号：US13967558

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yeu Tsai ,  Chia-Hui Lin ,  Ching-Yu Chen ,  Chui-Ya Peng

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76229

Abstract: A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.

Abstract translation: 公开了一种包括以下概述的操作的方法。 绝缘材料设置在半导体衬底上并在半导体衬底之上的多个沟槽内。 第一层形成在绝缘材料上。 去除第一层和绝缘材料。

公开(公告)号：US20240282638A1

公开(公告)日：2024-08-22

申请号：US18636384

申请日：2024-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Jaming Chang ,  Kai Hung Cheng ,  Chia-Hui Lin ,  Jei Ming Chen

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US20240120236A1

公开(公告)日：2024-04-11

申请号：US18306716

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Jung Kuo ,  Po-Cheng Shih ,  Wan Chen Hsieh ,  Zhen-Cheng Wu ,  Chia-Hui Lin ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/823481 ,  H01L27/0886

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

公开(公告)号：US20220328360A1

公开(公告)日：2022-10-13

申请号：US17852716

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Jaming Chang ,  Kai Hung Cheng ,  Chia-Hui Lin ,  Jei Ming Chen

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US11380593B2

公开(公告)日：2022-07-05

申请号：US17019475

申请日：2020-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Jaming Chang ,  Kai Hung Cheng ,  Chia-Hui Lin ,  Jei Ming Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US11195717B2

公开(公告)日：2021-12-07

申请号：US16983187

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Sheng Li ,  Chia-Hui Lin ,  Kai Hung Cheng ,  Yao-Hsu Sun ,  Wen-Cheng Wu ,  Bo-Cyuan Lu ,  Sung-En Lin ,  Tai-Chun Huang

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8238 ,  G03F7/09 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26

Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.