公开(公告)号：US06377074B1

公开(公告)日：2002-04-23

申请号：US09521418

申请日：2000-03-08

申请人： Takashi Kono ,  Katsuyoshi Mitsui

发明人： Takashi Kono ,  Katsuyoshi Mitsui

IPC分类号： H03K190175

CPC分类号： G11C5/147 ,  G05F1/465 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the present semiconductor integrated circuit device, a buffer is provided between a constant-current source circuit and an internal circuit that becomes a source of noise. The buffer controls the potential of an output node such that the potential of the output node becomes the bias potential. Even when noise is generated on the bias potential line when the internal circuit is in operation, the buffer dampens the noise. Thus, the noise generated in the internal circuit is prevented from adversely affecting the constant-current source circuit, and a stable operation of the internal circuit itself is achieved.

摘要翻译： 在本半导体集成电路器件中，在恒流源电路和成为噪声源的内部电路之间提供缓冲器。 缓冲器控制输出节点的电位，使得输出节点的电位变为偏置电位。 即使当内部电路运行时，在偏置电位线上产生噪声时，缓冲器也会抑制噪声。 因此，防止在内部电路中产生的噪声不利地影响恒流源电路，并且实现内部电路本身的稳定操作。

公开(公告)号：US06320810B1

公开(公告)日：2001-11-20

申请号：US09659832

申请日：2000-09-11

申请人： Takashi Kono ,  Katsuyoshi Mitsui

发明人： Takashi Kono ,  Katsuyoshi Mitsui

IPC分类号： G11C700

CPC分类号： G11C5/147 ,  G11C7/22 ,  G11C11/4074

摘要： A through-current Ic of a comparator circuit is switched in accordance with a response speed required with respect to a current consumption. Additionally, a through-current Is of a shifter circuit, which sends to the comparator circuit an output signal at an appropriate level transmitting a difference between an internal power supply potential Vdd and a reference potential Vref is switched according to the required response speed. When a device is in a standby state requiring a small current consumption in internal power supply potential Vdd, both through-currents Ic and Is are set small so that the whole current consumption can be further reduced.

摘要翻译： 根据相对于电流消耗所需的响应速度来切换比较器电路的直流电流Ic。 此外，根据所需的响应速度来切换向比较器电路发送传递内部电源电位Vdd和参考电位Vref之间的差的适当电平的输出信号的移相器电路Is。 当器件处于需要在内部电源电位Vdd中的小电流消耗的待机状态时，将两个贯通电流Ic和Is设定得较小，从而可以进一步降低整个电流消耗。

公开(公告)号：US06229753B1

公开(公告)日：2001-05-08

申请号：US09576229

申请日：2000-05-22

申请人： Takashi Kono ,  Katsuyoshi Mitsui

发明人： Takashi Kono ,  Katsuyoshi Mitsui

IPC分类号： G11C800

CPC分类号： G11C5/145

摘要： A Vpp level detecting circuit detects a potential on a Vpp trunk line which is provided commonly to a plurality of memory array banks for supplying a boosted potential thereto, and a boosted potential pump circuit supplies a current to the Vpp trunk line in accordance with a result of the detection. Since the position on the Vpp trunk line where the Vpp level detecting circuit performs the monitoring is substantially equally spaced from the respective memory blocks, an influence caused by an active state of the memory array bank can be suppressed during control of the potential on the Vpp trunk line.

摘要翻译： Vpp电平检测电路检测Vpp干线上的电位，该电位共同提供给多个存储器阵列组，用于向其提供升压电位，并且升压电位泵电路根据结果向Vpp中继线提供电流 的检测。 由于Vpp电平检测电路执行监视的Vpp中继线上的位置与各个存储块基本上相等间隔，所以可以在Vpp的电位的控制期间抑制由存储器阵列组的活动状态引起的影响 干线。

公开(公告)号：US6121806A

公开(公告)日：2000-09-19

申请号：US166909

申请日：1998-10-06

申请人： Takashi Kono ,  Takayuki Miyamoto ,  Katsuyoshi Mitsui ,  Shinichi Jinbo

发明人： Takashi Kono ,  Takayuki Miyamoto ,  Katsuyoshi Mitsui ,  Shinichi Jinbo

IPC分类号： G11C5/14 ,  G11C29/02 ,  G11C29/50 ,  H03K3/286

CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C5/143 ,  G11C5/147 ,  G11C11/401 ,  G11C2029/5004

摘要： A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.

摘要翻译： 一种电平调节电路，用于控制提供给诸如半导体器件的负载的电压，其包括电压电平检测电路，用于产生要输出到电压电平检测电路的一对参考电位值的参考电位产生电路，以及 用于绘制提供给负载的电压的监视器焊盘，其中分别使用参考电位值与电压进行比较，从而输出用于开始电压供应的信号和用于停止在通常情况下提供电压的信号 使用条件; 并且电压电平检测电路将参考电位值与电压或其他参考电位值中的任一个与测试条件下的一次电压进行比较，从而可以精确地调整参考电位产生电路以改变参考值 将电压值置于负载运行允许范围内的电位值。

公开(公告)号：US20110193640A1

公开(公告)日：2011-08-11

申请号：US13021047

申请日：2011-02-04

申请人： Tsukasa OISHI ,  Katsuyoshi Mitsui ,  Naoki Otani

发明人： Tsukasa OISHI ,  Katsuyoshi Mitsui ,  Naoki Otani

IPC分类号： H03L7/099

CPC分类号： H03B5/04 ,  H03L1/00 ,  H03L1/026

摘要： This invention provides a semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A temperature sensor detects the ambient temperature of the high speed OCO and a voltage sensor detects the operating voltage of the high speed OCO. The power supply module includes a BGR and generates the reference voltage, reference current, and operating voltage of the high speed OCO, based on a primary reference voltage which is output by the BGR. A flash memory stores a table specifying trimming codes for the reference voltage and reference current, related to an ambient temperature and an operating voltage of the high speed OCO. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to the detected ambient temperature and operating voltage.

摘要翻译： 本发明提供了一种半导体器件，其被设计为防止提供给高速OCO的参考电压和参考电流随着环境温度的变化和/或外部电源电压的变化而变化，并且减小电路面积 电源模块。 高速OCO输出高速时钟，其大小由参考电流和参考电压决定。 温度传感器检测高速OCO的环境温度，电压传感器检测高速OCO的工作电压。 电源模块包括BGR，并基于由BGR输出的主参考电压产生高速OCO的参考电压，参考电流和工作电压。 闪速存储器存储一个表格，该表格指定与环境温度和高速OCO的工作电压相关的参考电压和参考电流的修整代码。 逻辑单元根据与检测到的环境温度和工作电压相关的参考电压和参考电流调整代码调整参考电流和参考电压的值。

公开(公告)号：US07728678B2

公开(公告)日：2010-06-01

申请号：US12253636

申请日：2008-10-17

申请人： Katsuyoshi Mitsui

发明人： Katsuyoshi Mitsui

IPC分类号： H03L7/00 ,  H03L7/06

CPC分类号： H03L7/02 ,  H03L7/00

摘要： A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.

摘要翻译： 一种半导体器件包括：电压控制和振荡电路，其以根据第一控制电压的频率振荡以输出振荡信号;频率/电压转换电路，从所述电压控制和振荡电路接收所述振荡信号，并转换所述振荡频率 信号转换为电压，产生具有在由频率/电压转换电路转换的电压与先前产生的第二控制电压的电压之间的电平的新的第二控制电压的控制电压产生电路以及将第二 控制电压产生第一控制电压并将第一控制电压输出到电压控制和振荡电路。

公开(公告)号：US5407867A

公开(公告)日：1995-04-18

申请号：US948528

申请日：1992-09-22

申请人： Masanobu Iwasaki ,  Hiromi Itoh ,  Akira Tokui ,  Katsuyoshi Mitsui ,  Katsuhiro Tsukamoto

发明人： Masanobu Iwasaki ,  Hiromi Itoh ,  Akira Tokui ,  Katsuyoshi Mitsui ,  Katsuhiro Tsukamoto

IPC分类号： C23C14/02 ,  C23C14/56 ,  C23C16/02 ,  C23C16/54 ,  H01L21/465

CPC分类号： C23C14/568 ,  C23C14/022 ,  C23C16/0236 ,  C23C16/54 ,  Y10S438/913

摘要： A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface. As a result, an interface structure between the semiconductor substrate and the thin film can be controlled to be in a preferable state.

摘要翻译： 一种用于去除半导体衬底表面上的天然生长的氧化物膜和污染物，然后在清洁表面上形成薄膜的方法和设备。 将半导体基板放置在预处理室中，然后将氯化氢气体引入室中。 然后，在200℃〜700℃的温度下加热半导体衬底，用紫外线照射半导体衬底的表面，由此可以除去半导体衬底上的天然生长的氧化膜和其它污染物。 然后，通过CVD法或溅射法在半导体衬底的清洁表面上形成薄膜。 根据该方法，可以在低温下从半导体基板的表面去除天然氧化膜和其它污染物，并且可以在清洁的表面上形成薄膜。 结果，可以将半导体衬底和薄膜之间的界面结构控制在优选的状态。

公开(公告)号：US5378923A

公开(公告)日：1995-01-03

申请号：US909324

申请日：1992-07-06

申请人： Katsuyoshi Mitsui ,  Masahiro Shimizu

发明人： Katsuyoshi Mitsui ,  Masahiro Shimizu

IPC分类号： H01L27/12 ,  H01L21/338 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812 ,  H01L29/06 ,  H01L29/784

CPC分类号： H01L29/78612

摘要： Holes generated by impact ionization in a SOI-MOS transistor is removed from the channel region to improve the breakdown voltage between the source and drain. A channel region of the SOI-MOS transistor is formed of a p type silicon layer. A drain region is formed of an n type silicon layer. A source region adjacent to the channel region includes an n type germanium layer. The forbidden energy band gap width of the germanium is smaller than that of the silicon. The n type germanium layer is formed in at least a portion of the source region. This layer is formed by ion-implanting germanium into a portion of the silicon layer, or removing a portion of the silicon layer, followed by growing a germanium layer in an epitaxial manner thereabove.

摘要翻译： 在SOI-MOS晶体管中通过冲击电离产生的孔从沟道区域去除以改善源极和漏极之间的击穿电压。 SOI-MOS晶体管的沟道区域由p型硅层形成。 漏区由n型硅层形成。 与沟道区相邻的源极区包括n型锗层。 锗的禁带宽度窄于硅。 n型锗层形成在源区的至少一部分中。 该层通过将锗离子注入到硅层的一部分中，或者去除硅层的一部分，然后以其外延方式生长锗层而形成。

公开(公告)号：US5296401A

公开(公告)日：1994-03-22

申请号：US973250

申请日：1992-11-09

申请人： Katsuyoshi Mitsui ,  Shigeki Komori

发明人： Katsuyoshi Mitsui ,  Shigeki Komori

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L21/70

CPC分类号： H01L29/42376 ,  H01L21/823864 ,  H01L29/78 ,  H01L29/7836

摘要： In a CMOS semiconductor device, a pMOS transistor and an nMOS transistor are formed on a single substrate. Each of the source/drain regions of the nMOS transistor and the pMOS transistor has LDD structure composed of a combination of a low concentration impurity region and a high concentration impurity region. The low concentration impurity region of the LDD structure of the pMOS transistor is formed in a self-align manner by ion implantation using a sidewall spacer with relatively thick film thickness. The low concentration impurity region of the LDD structure of the nMOS transistor is formed in a self-align manner by ion implantation using a relatively thin sidewall spacer as a mask. The sidewall spacer with thick film thickness of the pMOS transistor restrains that the channel between the source/drain regions is shortened due to thermal diffusion to cause punch through. As for the sidewall spacer of the nMOS transistor, its film thickness is selected to effectively restrain hot carrier effect in the vicinity of the drain and restrain degradation of current handling capability due to parasitic resistance to the minimum.

摘要翻译： 在CMOS半导体器件中，在单个衬底上形成pMOS晶体管和nMOS晶体管。 nMOS晶体管和pMOS晶体管的源极/漏极区域中的每一个具有由低浓度杂质区域和高浓度杂质区域的组合构成的LDD结构。 pMOS晶体管的LDD结构的低浓度杂质区域通过使用具有相对厚的膜厚度的侧壁间隔件的离子注入以自对准的方式形成。 nMOS晶体管的LDD结构的低浓度杂质区域通过使用相对较薄的侧壁间隔物作为掩模的离子注入以自对准的方式形成。 具有pMOS晶体管的厚膜厚度的侧壁隔离层限制了源极/漏极区域之间的沟道由于热扩散而被缩短以引起穿通。 对于nMOS晶体管的侧壁间隔物，其膜厚度被选择为有效地抑制在漏极附近的热载流子效应，并且抑制由寄生电阻降到最小的电流处理能力的劣化。

公开(公告)号：US5183771A

公开(公告)日：1993-02-02

申请号：US732541

申请日：1991-07-19

申请人： Katsuyoshi Mitsui ,  masahide Inuishi

发明人： Katsuyoshi Mitsui ,  masahide Inuishi

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.

摘要翻译： 在具有LDD和自对准硅化物结构的MIS晶体管中，高和低杂质浓度源极/漏极区域之间的边界位置和源极/漏极区域上的自对准硅化物层的位置在制造期间被独立地控制，使用双 门侧壁结构。 因此，改善的MIS晶体管相对于双栅极侧壁结构的界面在其与控制栅电极之间或之后的高杂质浓度源极/漏极区域之间具有边界。