公开(公告)号：US07084477B2

公开(公告)日：2006-08-01

申请号：US10600771

申请日：2003-06-23

申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

摘要翻译： 为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

公开(公告)号：US06943076B2

公开(公告)日：2005-09-13

申请号：US09943843

申请日：2001-08-30

申请人： Tomio Iwasaki ,  Hideo Miura ,  Hiroyuki Ohta ,  Hiroshi Moriya

发明人： Tomio Iwasaki ,  Hideo Miura ,  Hiroyuki Ohta ,  Hiroshi Moriya

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10882 ,  H01L29/4966 ,  H01L29/513

摘要： Gate insulation films each containing titanium oxide as a primary constituent material are formed on one major surface of a semiconductor substrate. Gate electrode films are formed in contact with the gate insulation films. The gate electrode films contain ruthenium oxide or alternatively iridium oxide as a primary constituent material. In order to prevent electrically conductive elements from diffusing into titanium oxide of the gate insulation films, ruthenium oxide or iridium oxide is effectively used as a primary constituent material of the gate electrodes. A semiconductor device can be realized in which occurrence of a leak current is suppressed by increasing a physical film thickness while sustaining desired dielectric characteristic.

摘要翻译： 在半导体衬底的一个主表面上形成各自含有氧化钛作为主要构成材料的栅极绝缘膜。 形成与栅极绝缘膜接触的栅极电极膜。 栅极电极膜含有氧化钌或氧化铱作为主要构成材料。 为了防止导电元件扩散到栅极绝缘膜的氧化钛中，氧化钌或氧化铱被有效地用作栅电极的主要构成材料。 可以实现半导体器件，其中通过在保持期望的介电特性的同时增加物理膜厚度来抑制泄漏电流的发生。

公开(公告)号：US06686274B1

公开(公告)日：2004-02-03

申请号：US09787743

申请日：2001-06-08

申请人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

发明人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76877

摘要： In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.

摘要翻译： 在具有钴硅化物膜的半导体器件中，钴硅化物膜中至少含有镍或铁，以防止附着于薄膜变薄的电阻上升。

公开(公告)号：US06521932B1

公开(公告)日：2003-02-18

申请号：US09525029

申请日：2000-03-14

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

公开(公告)号：US06639263B2

公开(公告)日：2003-10-28

申请号：US10255714

申请日：2002-09-27

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

摘要翻译： 本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。 根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

公开(公告)号：US20060214254A1

公开(公告)日：2006-09-28

申请号：US11443226

申请日：2006-05-31

申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

摘要： To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

摘要翻译： 为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

公开(公告)号：US06965140B2

公开(公告)日：2005-11-15

申请号：US10669330

申请日：2003-09-25

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/52 ,  H01L23/532 ,  H01L27/00 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

摘要翻译： 本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。 根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

公开(公告)号：US07701062B2

公开(公告)日：2010-04-20

申请号：US11834081

申请日：2007-08-06

申请人： Tomio Iwasaki ,  Hideo Miura

发明人： Tomio Iwasaki ,  Hideo Miura

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}

摘要翻译： 提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触 与导体膜。 在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差， ，构成具有相邻膜的最小自由能的平面的矩形单元电池，矩形单位电池的长边，bp之间的差异为{| ap-an | / ap}×100 = A（％） 构成具有相邻膜的最小自由能的构成平面的矩形单位电池的导体膜和长边bn的最小自由能的平面{| bp-bn | / bp}×100 = B （％）满足{A + B×（ap / bp）} <13的不等式。 在此，导体膜的扩散被延迟。

公开(公告)号：US20060183324A1

公开(公告)日：2006-08-17

申请号：US11392540

申请日：2006-03-30

申请人： Tomio Iwasaki ,  Hideo Miura

发明人： Tomio Iwasaki ,  Hideo Miura

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}

摘要翻译： 提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与 导体膜。 在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即 _{n x100 = A（％）和构成该矩阵单位单元的长边，b}

P 之间的差异 构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。 在此，导体膜的扩散被延迟。}

公开(公告)号：US07030493B2

公开(公告)日：2006-04-18

申请号：US10878018

申请日：2004-06-29

申请人： Tomio Iwasaki ,  Hideo Miura

发明人： Tomio Iwasaki ,  Hideo Miura

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}

摘要翻译： 提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与 导体膜。 在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即 _{n x100 = A（％）和构成该矩阵单位单元的长边，b}

P 之间的差异 构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。 在此，导体膜的扩散被延迟。}