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    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20120313112A1

    公开(公告)日：2012-12-13

    申请号：US13490208

    申请日：2012-06-06

    申请人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

    发明人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

    IPC分类号： H01L29/161

    CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7813

    摘要： A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm−3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.

    摘要翻译： MOSFET包括碳化硅衬底，由碳化硅制成的漂移层，并且包括相对于{0001}面具有50°以上且65°以下的偏离角的主表面，以及形成在 并与漂移层的主表面接触。 漂移层包括形成为包括与栅氧化膜接触的区域的p型体区。 p型体区的杂质浓度为5×10 16 cm -3以上。 在垂直于漂移层的厚度方向的方向上彼此分离的p导电类型的多个p型区域布置在位于p型体区域和碳化硅衬底之间的漂移层中的区域中。

    SEMICONDUCTOR DEVICE
    15.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20120193643A1

    公开(公告)日：2012-08-02

    申请号：US13364174

    申请日：2012-02-01

    申请人： Takeyoshi MASUDA ,  Toru Hiyoshi ,  Keiji Wada

    发明人： Takeyoshi MASUDA ,  Toru Hiyoshi ,  Keiji Wada

    IPC分类号： H01L29/16

    CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068

    摘要： A MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a p type body region in which an inversion layer is formed when the gate electrode is fed with a voltage. The inversion layer has an electron mobility μ dependent more strongly on an acceptor concentration Na of a channel region of the p type body region, as compared with a dependency of the electron mobility μ being proportional to the reciprocal of the acceptor concentration Na. The acceptor concentration Na in the channel region of the p type body region is not less than 1×1016 cm−3 and not more than 2×1018 cm3. The channel length (L) is equal to or smaller than 0.43 μm. The channel length (L) is equal to or longer than a spreading width d of a depletion layer in the channel region. The spreading width d is expressed by d=D·Na−C.

    摘要翻译： MOSFET包括碳化硅衬底，有源层，栅极氧化膜和栅电极。 有源层包括p型体区，当栅电极被馈送电压时，形成反型层。 与电子迁移率μ与受主浓度Na的倒数成比例的电子迁移率μ的依赖性相比，反型层具有更强地依赖于p型体区的沟道区的受主浓度Na的电子迁移率μ。 p型体区的通道区域中的受主浓度Na不小于1×1016cm-3且不大于2×1018cm 3。 通道长度（L）等于或小于0.43μm。 通道长度（L）等于或大于沟道区域中的耗尽层的扩展宽度d。 扩展宽度d由d = D·Na-C表示。

    Silicon carbide semiconductor device and method for manufacturing the same
    17.
    发明授权
    Silicon carbide semiconductor device and method for manufacturing the same 有权
    碳化硅半导体器件及其制造方法

    公开(公告)号：US09012335B2

    公开(公告)日：2015-04-21

    申请号：US13520702

    申请日：2011-03-04

    申请人： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

    发明人： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

    IPC分类号： H01L21/31 ,  H01L21/82 ,  H01L21/04 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L29/04 ,  H01L29/16

    CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/8213 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/94

    摘要： A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.

    摘要翻译： 提供一种具有优异的包括沟道迁移率的电特性的碳化硅半导体器件及其制造方法。 制造碳化硅半导体器件的方法包括：制备碳化硅半导体膜的外延层形成步骤; 在所述半导体膜的表面上形成氧化膜的栅极绝缘膜形成工序; 在含氮气氛中对形成有氧化膜的半导体膜进行热处理的氮退火工序; 以及后处理工序，在氮退火工序后，在含有惰性气体的气氛中对形成有氧化膜的半导体膜进行后热处理。 后热处理工序中的热处理温度高于氮退火工序中的热处理温度，低于氧化膜的熔点。

    Silicon carbide semiconductor device
    19.
    发明授权
    Silicon carbide semiconductor device 有权
    碳化硅半导体器件

    公开(公告)号：US08686435B2

    公开(公告)日：2014-04-01

    申请号：US13434233

    申请日：2012-03-29

    申请人： Takeyoshi Masuda ,  Toru Hiyoshi ,  Keiji Wada

    发明人： Takeyoshi Masuda ,  Toru Hiyoshi ,  Keiji Wada

    IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/12 ,  H01L29/78

    CPC分类号： H01L21/28 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

    摘要： A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm−3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

    摘要翻译： 在基板的主表面上外延形成碳化硅层。 碳化硅层设置有具有相对于主表面倾斜的侧壁的沟槽。 侧壁相对于{0001}面具有不小于50°且不超过65°的偏离角。 栅极绝缘膜设置在碳化硅层的侧壁上。 碳化硅层包括：具有第一导电类型且面对栅电极的主体区域，栅极绝缘膜介于其间; 以及一对由身体区域彼此隔开并具有第二导电类型的区域。 体区的杂质密度为5×1016 cm -3以上。 这允许在抑制信道移动性的降低的同时增加设置阈值电压的自由度。