公开(公告)号：US5670894A

公开(公告)日：1997-09-23

申请号：US754029

申请日：1996-12-04

Applicant: Toru Takaishi ,  Tetsu Tanizawa

Inventor： Toru Takaishi ,  Tetsu Tanizawa

IPC: H03K19/003 ,  H03K5/02 ,  H03K17/16 ,  H03K19/0948 ,  H03K19/017

CPC classification number: H03K19/00361

Abstract: The present invention is to provide an output circuit, for a semiconductor circuit, capable of increasing the rise or fall time of an output signal without reducing the operating frequency of the output circuit, and thus effectively preventing occurrence of a malfunction due to an undesired change in the output signal caused by ringing, noise, or reflection occurring at the transition of the output signal. In the structure of present invention, an output circuit for a semiconductor circuit includes an input circuit, an output circuit including a transistor, and a control signal control circuit that lies between the input circuit and output circuit, outputs a control signal for use in driving the transistor in the output circuit, and changes the control signal according to a function of time.

Abstract translation: 本发明提供一种半导体电路的输出电路，其能够在不降低输出电路的工作频率的情况下增加输出信号的上升或下降时间，并且因此有效地防止由于不希望的变化引起的故障的发生 在由输出信号的转变发生的振铃，噪声或反射引起的输出信号中。 在本发明的结构中，半导体电路的输出电路包括输入电路，包括晶体管的输出电路和位于输入电路和输出电路之间的控制信号控制电路，输出用于驱动的​​控制信号 输出电路中的晶体管，并根据时间的函数改变控制信号。

公开(公告)号：US5436485A

公开(公告)日：1995-07-25

申请号：US365173

申请日：1994-12-28

Applicant: Junichi Shikatani ,  Tetsu Tanizawa ,  Mitsugu Naito

Inventor： Junichi Shikatani ,  Tetsu Tanizawa ,  Mitsugu Naito

IPC: H01L27/118 ,  H01L27/02 ,  H01L27/10

CPC classification number: H01L27/11807 ,  Y10S257/909

Abstract: A master-slice type semiconductor integrated circuit device includes a first transistor, and a second transistor. The first and second transistors are arranged side by side in a first direction. The first and second transistors respectively have first and second gate electrodes extending in a second direction perpendicular to the first direction. The first gate electrode has a first portion in which two gate contacts arranged in the first direction can be made. The second gate electrode has a second portion in which two gate contacts arranged in the first direction can be made.

Abstract translation: 主切片式半导体集成电路器件包括第一晶体管和第二晶体管。 第一和第二晶体管沿第一方向并排布置。 第一和第二晶体管分别具有在垂直于第一方向的第二方向上延伸的第一和第二栅电极。 第一栅电极具有第一部分，其中可以制造沿第一方向布置的两个栅极触点。 第二栅电极具有第二部分，其中可以制造沿第一方向布置的两个栅极触点。

公开(公告)号：US4816705A

公开(公告)日：1989-03-28

申请号：US53568

申请日：1987-05-21

Applicant: Osam Ohba ,  Tetsu Tanizawa

Inventor： Osam Ohba ,  Tetsu Tanizawa

IPC: H03K17/04 ,  H03K19/00 ,  H03K19/013 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/60 ,  H03K19/094

CPC classification number: H03K19/09448 ,  H03K19/001 ,  H03K19/0136

Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit is composed of a first stage comprising a complementary MIS-FET, and an output stage comprising complementary bipolar transistors or complementary vertical FETs. The output stage is provided with pull-up and pull-down elements, which pull up or pull down the amplitude of the output signal almost equal to that of the power supply voltages. Accordingly, the lack of sufficient amplitude in the conventional Bi-MIS circuit to drive the C-MIS circuit is improved, and it secures the stable operation of C-MIS logic circuits.

Abstract translation: 公开了具有大功率处理能力，高开关速度并且仍然具有低功耗的互补逻辑电路。 电路由包括互补MIS-FET的第一级和包括互补双极晶体管或互补垂直FET的输出级组成。 输出级配有上拉和下拉元件，其上拉或下拉输出信号的幅度几乎等于电源电压的幅度。 因此，改善了传统的Bi-MIS电路中驱动C-MIS电路的足够的幅度，并且确保了C-MIS逻辑电路的稳定操作。

公开(公告)号：US4602339A

公开(公告)日：1986-07-22

申请号：US535832

申请日：1983-09-26

Applicant: Satoshi Aihara ,  Tetsu Tanizawa

Inventor： Satoshi Aihara ,  Tetsu Tanizawa

IPC: G06F17/50 ,  H01L21/82 ,  H01L27/118 ,  H01L27/02 ,  G06F15/60

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  H01L21/82 ,  H01L27/118

Abstract: A method of manufacturing a master-slice integrated circuit device, implemented based on a total circuit diagram, including one or more logic blocks, each including a plurality of basic logic blocks such as flip-flops, NAND gates, and the like. The total circuit diagram is reformed by deleting unused basic logic blocks in each of the logic blocks whose output terminals are not used, by deleting unused wirings and other unused basic logic blocks whose output terminals are not connected to any basic logic blocks as a result of the deletion of the basic logic blocks, and by sequentially deleting unused basic logic blocks and unused wirings in the same manner, so as to retain only those basic logic blocks actually used as effective basic logic blocks. The circuit patterns of the master slice integrated circuit device are produced by using the total circuit diagram thus reformed.

Abstract translation: 一种制造母片集成电路器件的方法，其基于包括一个或多个逻辑块的总电路图实现，每个逻辑块包括多个基本逻辑块，诸如触发器，NAND门等。 总电路图通过删除未使用输出端的每个逻辑块中的未使用的基本逻辑块，通过删除未使用的布线和其他未使用的基本逻辑块，其输出端子未连接到任何基本逻辑块，由此进行改造 基本逻辑块的删除，以及以相同的方式依次删除未使用的基本逻辑块和未使用的布线，以便仅保留实际用作有效基本逻辑块的基本逻辑块。 主片集成电路器件的电路图案通过使用如此改造的总电路图来产生。

公开(公告)号：US4562364A

公开(公告)日：1985-12-31

申请号：US423716

申请日：1982-09-27

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H03K19/00 ,  H03K19/088 ,  H03K17/16

CPC classification number: H03K19/001 ,  H03K19/088

Abstract: A TTL circuit comprising an inverted signal output transistor (Tr.sub.4) and an off buffer circuit (Tr.sub.2, Tr.sub.3), alternately turned on and off in response to an input signal, to provide an inverted output. According to the invention, two driving circuits for driving the inverted signal output transistor and the off buffer circuit are separately provided. The threshold voltage of the circuit for driving the off buffer circuit is lower than the threshold voltage of the circuit for driving the inverted signal output transistor, whereby no transient current flows through the off buffer circuit and the inverted signal output transistor.

Abstract translation: 包括反相信号输出晶体管（Tr4）和截止缓冲电路（Tr2，Tr3）的TTL电路根据输入信号交替地导通和截止，以提供反相输出。 根据本发明，分别提供用于驱动反相信号输出晶体管和截止缓冲电路的两个驱动电路。 用于驱动截止缓冲电路的电路的阈值电压低于用于驱动反相信号输出晶体管的电路的阈值电压，由此暂态电流不通过截止缓冲电路和反相信号输出晶体管。

公开(公告)号：US07774580B2

公开(公告)日：2010-08-10

申请号：US11077561

申请日：2005-03-11

Applicant: Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F15/8007

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract translation: 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

公开(公告)号：US5848154A

公开(公告)日：1998-12-08

申请号：US502354

申请日：1995-07-14

Applicant: Nobuhiko Nishio ,  Tetsu Tanizawa ,  Kiyokatsu Iijima ,  Muneharu Gotou

Inventor： Nobuhiko Nishio ,  Tetsu Tanizawa ,  Kiyokatsu Iijima ,  Muneharu Gotou

IPC: G06F1/00 ,  G06F11/34 ,  G06F21/00 ,  H04N5/85 ,  H04N9/804 ,  H04N9/806 ,  H04L9/00 ,  H04L9/06

CPC classification number: H04N9/8042 ,  G06F21/10 ,  G06F11/3409 ,  G06F2201/88 ,  G06F2221/2135 ,  H04N5/85 ,  H04N9/8063

Abstract: A DES decrypting unit decrypts video data frames encrypted and compressed based on MPEG standards, when receiving them. The decrypted video data frames are expanded one by one in a MPEG expansion circuit. Each time the single frame is expanded, the MPEG expansion circuit outputs a completion-of-frame-expansion signal to a host control CPU. The host control CPU counts the completion-of-frame-expansion signals and reduces an accounting count value in an accounting data memory in accordance with this count value. The host control CPU output character pattern image data from a pattern generator when the accounting count value becomes 0. The character pattern image data is superimposed on a video signal in an adder circuit.

Abstract translation: DES解密单元在接收它们时解密基于MPEG标准加密和压缩的视频数据帧。 解密的视频数据帧在MPEG扩展电路中逐个扩展。 每次扩展单个帧时，MPEG扩展电路向主机控制CPU输出完成帧扩展信号。 主机控制CPU根据该计数值计算帧完成信号，并减少会计数据存储器中的记帐计数值。 当计费计数值为0时，主机控制CPU从模式发生器输出字符图案图像数据。字符图案图像数据叠加在加法器电路中的视频信号上。

公开(公告)号：US5581109A

公开(公告)日：1996-12-03

申请号：US392159

申请日：1995-02-22

Applicant: Kuniyuki Hayashi ,  Masaya Kitagawa ,  Tetsu Tanizawa

Inventor： Kuniyuki Hayashi ,  Masaya Kitagawa ,  Tetsu Tanizawa

IPC: H01L21/822 ,  H01L23/528 ,  H01L27/04 ,  H01L29/00

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10S257/909

Abstract: A semiconductor device includes a semiconductor chip, an I/O-cell circuit having a transistor-array part. The semiconductor device further includes a first group of bonding pads and a second group of bonding pads. The first group of bonding pads is connected with the I/O-cell circuit and is formed in a first pad-forming area arranged along an outer side of the transistor-array part in the I/O-cell circuit. And the second group of bonding pads is connected with the I/O-cell circuit and is formed in a second pad-forming area along an inner side of the transistor-array part in the I/O-cell circuit.

Abstract translation: 半导体器件包括半导体芯片，具有晶体管阵列部分的I / O单元电路。 半导体器件还包括第一组焊盘和第二组焊盘。 第一组接合焊盘与I / O单元电路连接，并且形成在沿着I / O单元电路中的晶体管阵列部分的外侧布置的第一焊盘形成区域中。 并且第二组接合焊盘与I / O单元电路连接，并且沿着I / O单元电路中的晶体管阵列部分的内侧形成在第二焊盘形成区域中。

公开(公告)号：US5388055A

公开(公告)日：1995-02-07

申请号：US756017

申请日：1991-09-06

Applicant: Tetsu Tanizawa ,  Hideo Tokuda ,  Shigenori Ichinose ,  Katuzi Hirochi ,  Takehito Doi

Inventor： Tetsu Tanizawa ,  Hideo Tokuda ,  Shigenori Ichinose ,  Katuzi Hirochi ,  Takehito Doi

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02 ,  H01L23/48

CPC classification number: H01L23/5286 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2924/0002

Abstract: A semiconductor integrated circuit includes a substrate which has a predetermined width in a first direction and a predetermined length in a second direction which is approximately perpendicular to the first direction, a plurality of cells which are provided on the substrate and are grouped into a plurality of generally rectangular unit blocks, where each of the unit blocks are made up of cells having mutually different widths in the first direction but a common length in the second direction, first interconnections for supplying at least one power source voltage to the cells, where the first interconnections are provided independently for each unit block so as to supply the power source voltage in common to each of the cells making up the unit block, a row of first terminals of the cells, within each unit block, arranged in the first direction, a row of second terminals of the cells, within each unit block, arranged in the first direction an interconnection region at least including a region which is defined by the rows of the first and second terminals, and second interconnections which are provided within the interconnection region with respect to each unit block and connects the cells within the unit block.

Abstract translation: 一种半导体集成电路包括：基板，其在大致垂直于第一方向的第二方向上具有在第一方向上的预定宽度和预定长度;多个单元，设置在基板上，并被分组为多个 通常是矩形单位块，其中每个单位块由在第一方向上具有相互不同宽度但在第二方向上具有公共长度的单元组成，用于向单元提供至少一个电源电压的第一互连，其中第一 为每个单元块独立地提供互连，以便将构成单元块的每个单元的公共电源电压提供给每个单元块中的在第一方向上布置的单元的一行第一端子， 在每个单元块内的单元的第二端子排沿第一方向布置成至少包括a的互连区域 区域，其由第一和第二端子的行限定，以及第二互连，其相对于每个单位块设置在互连区域内并连接单元块内的单元。

公开(公告)号：US4791320A

公开(公告)日：1988-12-13

申请号：US897460

申请日：1986-08-18

Applicant: Mitsuya Kawata ,  Tetsu Tanizawa

Inventor： Mitsuya Kawata ,  Tetsu Tanizawa

IPC: H03K19/08 ,  H01L27/07 ,  H03K19/013 ,  H03K19/0944 ,  H03K19/01

CPC classification number: H03K19/09448 ,  H01L27/0716 ,  H03K19/0136

Abstract: A compound transistor type inverter, i.e., comprised of MIS and bipolar transistors, including, at the output stage thereof, an npn transistor operative to charge a load. The npn transistor can be quickly cut OFF by an additional transistor, and simultaneously, the additional transistor is operative to attain a quick discharge from the load. Still another additional transistor is employed, in a case where the inverter includes a pnp transistor, other than the npn transistor, at a ground side, which another additional transistor is operative to bypass the collector and emitter of the pnp transistor.

Abstract translation: 复合晶体管型逆变器，即由MIS和双极晶体管构成，在其输出级包括可操作地对负载充电的npn晶体管。 npn晶体管可以通过附加晶体管快速切断，并且同时，附加晶体管可操作以从负载获得快速放电。 在逆变器包括位于地侧的pnp晶体管（npn晶体管以外）的情况下，采用另外的另外的晶体管，另一个另外的晶体管用于旁路pnp晶体管的集电极和发射极。