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    Split gate memory cell fabrication and system
    13.
    发明授权
    Split gate memory cell fabrication and system 有权

    公开(公告)号：US11239346B2

    公开(公告)日：2022-02-01

    申请号：US16426222

    申请日：2019-05-30

    Applicant: Texas Instruments Incorporated

    Inventor： John Howard MacPeak ,  Douglas Ticknor Grider ,  Brian K. Kirkpatrick

    IPC: H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L27/11546 ,  H01L29/423 ,  H01L21/28

    Abstract: A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

    Hard mask for source/drain epitaxy control
    16.
    发明授权
    Hard mask for source/drain epitaxy control 有权
    用于源极/漏极外延控制的硬掩模

    公开(公告)号：US09224657B2

    公开(公告)日：2015-12-29

    申请号：US13960517

    申请日：2013-08-06

    Applicant: Texas Instruments Incorporated

    Inventor： David Gerald Farber ,  Tom Lii ,  Brian K. Kirkpatrick

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823807

    Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

    Abstract translation: 集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。 在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。 硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。 半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。 随后，从第二极性MOS晶体管去除硬掩模。

    HIGH-K / METAL GATE CMOS TRANSISTORS WITH TiN GATES
    17.
    发明申请
    HIGH-K / METAL GATE CMOS TRANSISTORS WITH TiN GATES 审中-公开
    具有TiN栅的高K /金属栅CMOS CMOS晶体管

    公开(公告)号：US20150287643A1

    公开(公告)日：2015-10-08

    申请号：US14724185

    申请日：2015-05-28

    Applicant: Texas Instruments Incorporated

    Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

    IPC: H01L21/8238 ,  H01L21/3213 ,  H01L21/477 ,  H01L21/28

    CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

    Abstract translation: 具有厚度大于4.85eV的功函数的厚TiN金属栅的集成电路，并具有工作功能小于4.25eV的薄TiN金属栅。 具有替代栅极PMOS TiN金属栅极晶体管的集成电路，其功函数大于4.85eV，并具有功函数小于4.25eV的替代栅极NMOS TiN金属栅极晶体管。 具有栅极第一PMOS TiN金属栅极晶体管的集成电路，其功函数大于4.85eV，并具有功函数小于4.25eV的栅极第一NMOS TiN金属栅极晶体管。

    INNER L-SPACER FOR REPLACEMENT GATE FLOW
    18.
    发明申请
    INNER L-SPACER FOR REPLACEMENT GATE FLOW 有权
    内置L型间隔器，用于更换门流

    公开(公告)号：US20150069516A1

    公开(公告)日：2015-03-12

    申请号：US14022317

    申请日：2013-09-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chet Vernon LENOX ,  Seung-Chul SONG ,  Brian K. Kirkpatrick

    IPC: H01L21/8234 ,  H01L27/092

    CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

    Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

    Abstract translation: 通过去除牺牲栅极电介质层和牺牲栅极以形成栅极腔来形成集成电路。 在栅腔中形成保形电介质第一衬垫，并且在第一衬垫上形成共形第二衬垫。 第一蚀刻从栅极腔的底部去除第二衬垫，使第二衬垫的材料留在栅腔的侧壁上。 第二蚀刻从第二衬垫暴露的栅腔的底部去除第一衬垫，在栅腔的侧壁上的第二衬垫下方留下第一衬垫的底部上的第一衬垫的底部的材料。 第三蚀刻从栅极腔去除第二衬垫，在栅极腔中留下第一衬里的L形间隔物。 永久性栅极介电层和置换栅极形成在栅极腔中。

    HARD MASK FOR SOURCE/DRAIN EPITAXY CONTROL
    19.
    发明申请
    HARD MASK FOR SOURCE/DRAIN EPITAXY CONTROL 有权
    用于源/排水外挂控制的硬掩模

    公开(公告)号：US20150044830A1

    公开(公告)日：2015-02-12

    申请号：US13960517

    申请日：2013-08-06

    Applicant: Texas Instruments Incorporated

    Inventor： David Gerald Farber ,  Tom Lii ,  Brian K. Kirkpatrick

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823807

    Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

    Abstract translation: 集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。 在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。 硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。 半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。 随后，从第二极性MOS晶体管去除硬掩模。

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