公开(公告)号：US20210328595A1

公开(公告)日：2021-10-21

申请号：US16850597

申请日：2020-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy NURANI ,  Joseph Palackal MATHEW ,  Prasanth K ,  Visvesvaraya Appala PENTAKOTA ,  Shagun DUSAD

IPC: H03M1/12 ,  G11C27/02

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

公开(公告)号：US12206424B2

公开(公告)日：2025-01-21

申请号：US17899149

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Prasanth K ,  Rahul Sharma

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/16

Abstract: An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.

公开(公告)号：US20240106450A1

公开(公告)日：2024-03-28

申请号：US18090997

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Rajashekar Goroju ,  Prasanth K ,  Dileepkumar Ramesh Bhat ,  Rahul Sharma

IPC: H03M1/12

CPC classification number: H03M1/1245

Abstract: An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.

公开(公告)号：US11916567B2

公开(公告)日：2024-02-27

申请号：US17570658

申请日：2022-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

CPC classification number: H03M1/1245 ,  G11C27/02 ,  H03M1/121

Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

公开(公告)号：US20220247420A1

公开(公告)日：2022-08-04

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US11316525B1

公开(公告)日：2022-04-26

申请号：US17158526

申请日：2021-01-26

Applicant: Texas Instruments Incorporated

Inventor： Visvesvaraya Appala Pentakota ,  Narasimhan Rajagopal ,  Chirag Chandrahas Shetty ,  Prasanth K ,  Neeraj Shrivastava ,  Eeshan Miglani ,  Jagannathan Venkataraman

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/12

Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.

公开(公告)号：US11277145B2

公开(公告)日：2022-03-15

申请号：US16850597

申请日：2020-04-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy Nurani ,  Joseph Palackal Mathew ,  Prasanth K ,  Visvesvaraya Appala Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  G11C27/02

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.