公开(公告)号：US09548298B1

公开(公告)日：2017-01-17

申请号：US14942979

申请日：2015-11-16

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L21/338 ,  H01L27/06 ,  H01L29/732 ,  H01L21/8238 ,  H01L21/8222

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Abstract translation: 集成电路包括NMOS晶体管，PMOS晶体管和垂直双极晶体管。 垂直双极晶体管具有在本征基极的表面边界处具有至少25meV高的带势垒的本征基极，除了在与发射极的发射极 - 基极结之外，并且除了在与集电极的基极 - 集电极结之外。 本征碱可以被具有比本征碱更高的掺杂剂密度的外在碱基侧向包围，其中较高的掺杂剂密度在本征碱的侧表面提供带阻挡。 栅极可以设置在与发射极相邻的本征基极的顶表面边界上的栅极电介质层上。 栅极被配置为在栅极电介质层的正下方积聚本征基极，从而在本征基极的顶部表面边界提供带状屏障。

公开(公告)号：US20220189949A1

公开(公告)日：2022-06-16

申请号：US17684774

申请日：2022-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

公开(公告)号：US11249130B2

公开(公告)日：2022-02-15

申请号：US15859244

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuguo Wang ,  Steven Loveless ,  Tathagata Chatterjee ,  Jerry Doorenbos

IPC: G01R31/26

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US10571511B2

公开(公告)日：2020-02-25

申请号：US16130035

申请日：2018-09-13

Applicant: Texas Instruments Incorporated

Inventor： Alex Paikin ,  Colin Johnson ,  Tathagata Chatterjee ,  Sameer Pendharkar

IPC: G01R31/10 ,  G01R31/26 ,  G01R31/28

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US20170141101A1

公开(公告)日：2017-05-18

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L29/45 ,  H01L29/417 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.