公开(公告)号：US07439135B2

公开(公告)日：2008-10-21

申请号：US11308542

申请日：2006-04-04

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L29/7827 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

摘要翻译： 一种用于形成绝缘体上半导体沟槽器件的体接触的结构和方法。 该方法包括：在基板的顶表面上形成一组心轴，该组心轴的每个心轴布置在多边形的不同角上并且在衬底的顶表面上方延伸，该心轴组中的多个心轴 等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件，每个相邻的一对心轴的侧壁间隔件彼此合并并且形成在多边形的内部区域中限定开口的不间断的壁， 开口 蚀刻开口中的衬底中的接触沟槽; 以及用导电材料填充接触沟槽以形成接触。

公开(公告)号：US20080083941A1

公开(公告)日：2008-04-10

申请号：US11538982

申请日：2006-10-05

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1207 ,  H01L29/78

摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.

摘要翻译： 公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。 一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。 该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。 在一个实施例中，带是硅化物带。

公开(公告)号：US20080048259A1

公开(公告)日：2008-02-28

申请号：US11466480

申请日：2006-08-23

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

IPC分类号： H01L27/12

CPC分类号： H01L29/78603 ,  H01L29/66772 ,  H01L29/78609

摘要： A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower layer of silicon and an upper layer of silicon; and wherein silicon has a transmittance of at least 95% at the selected wavelength and silicon dioxide has a transmittance of less than 80% at the selected wavelength.

摘要翻译： 一种减少绝缘体上硅衬底的掩埋氧化物层缺陷的方法和结构。 该方法包括：产生所选波长的红外辐射束; 将绝缘体上硅衬底暴露于所述红外辐射束，所述衬底包括在下层硅和硅上层之间的掩埋二氧化硅层; 并且其中硅在所选波长处具有至少95％的透射率，并且二氧化硅在所选择的波长处具有小于80％的透射率。

公开(公告)号：US20070249144A1

公开(公告)日：2007-10-25

申请号：US11820713

申请日：2007-06-19

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L21/30

CPC分类号： H01L29/66772 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76254 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the single-crystal semiconductor region. The outer surface of the first wafer can then be bonded to the outer surface of a second wafer having a second single-crystal semiconductor region to form a bonded wafer having a bulk single-crystal semiconductor region, a buried dielectric layer overlying the bulk single-crystal semiconductor region, and a single-crystal semiconductor-on-insulator layer overlying the buried dielectric layer. The dielectric filled trenches may extend upwardly from the buried dielectric layer into the single-crystal semiconductor-on-insulator layer. The thickness of the semiconductor-on-insulator layer may then be reduced until uppermost surfaces of at least some of the dielectric filled trenches are at least partially exposed.

摘要翻译： 提供了一种用于形成接合的SOI晶片的方法，其中具有单晶半导体区域的第一晶片具有设置在第一晶片的外表面的第一电介质层和从外表面向内延伸的多个电介质填充的沟槽 单晶半导体区域。 然后可以将第一晶片的外表面接合到具有第二单晶半导体区域的第二晶片的外表面，以形成具有大块单晶半导体区域的接合晶片，覆盖大块单晶半导体区域的掩埋电介质层， 晶体半导体区域和覆盖在掩埋介电层上的绝缘体上单层半导体层。 电介质填充的沟槽可以从掩埋的介电层向上延伸到绝缘体上的单晶半导体层中。 然后可以减小绝缘体上半导体层的厚度，直到至少一些电介质填充沟槽的最上表面至少部分露出。

公开(公告)号：US20070189057A1

公开(公告)日：2007-08-16

申请号：US11306749

申请日：2006-01-10

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack Mandelman ,  Carl Radens ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack Mandelman ,  Carl Radens ,  Geng Wang

IPC分类号： G11C11/24

CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

摘要翻译： 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。 这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。 第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。 在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

公开(公告)号：US07247905B2

公开(公告)日：2007-07-24

申请号：US10813352

申请日：2004-03-30

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

摘要翻译： 本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。 具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中 位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于 第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

公开(公告)号：US07223653B2

公开(公告)日：2007-05-29

申请号：US10710045

申请日：2004-06-15

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L29/945

摘要： A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A dopant source layer is formed along the lower portion of the trench sidewall, the dopant source layer not being disposed along the upper portion of the trench sidewall. A layer is formed to cover the upper portion of the trench sidewall. Annealing is then performed to drive a dopant from the dopant source layer into the semiconductor substrate adjacent to the lower portion of the trench sidewall.

摘要翻译： 提供了一种在半导体衬底中制造掩埋板区域的方法。 根据这种方法，在半导体衬底中形成沟槽，沟槽具有沟槽侧壁，侧壁包括上部，下部设置在上部下方。 掺杂剂源层沿着沟槽侧壁的下部形成，掺杂剂源层不沿着沟槽侧壁的上部设置。 形成覆盖沟槽侧壁的上部的层。 然后进行退火以将掺杂剂从掺杂剂源层驱动到与沟槽侧壁的下部相邻的半导体衬底中。

公开(公告)号：US20070080440A1

公开(公告)日：2007-04-12

申请号：US11469039

申请日：2006-08-31

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L23/06 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

公开(公告)号：US20070047293A1

公开(公告)日：2007-03-01

申请号：US11161962

申请日：2005-08-24

申请人： Jack Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens ,  Geng Wang

发明人： Jack Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens ,  Geng Wang

IPC分类号： G11C11/24

CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：US20060175660A1

公开(公告)日：2006-08-10

申请号：US10906238

申请日：2005-02-10

申请人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Gary Bronner ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。