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    Delay Calculation Method, A Data Processing Program and A Computer Program Product for Routing of Wires of an Electronic Circuit
    11.
    发明申请
    Delay Calculation Method, A Data Processing Program and A Computer Program Product for Routing of Wires of an Electronic Circuit 有权
    延迟计算方法，数据处理程序和电子线路布线计算机程序产品

    公开(公告)号：US20090013293A1

    公开(公告)日：2009-01-08

    申请号：US12166012

    申请日：2008-07-01

    申请人： Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Punitz

    发明人： Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Punitz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin (P0; P30) and a receiving pin (P1-P19; P32-P42) being coupled by at least one loop (40, 50; 60, 70, 80), said loop (40, 50; 60, 70, 80) comprising a first branching path (BP40a, BP50a) and a second branching path (BP40b, BP50b) electrically parallel to said first branching path (BP40a, BP50a), wherein at least a first and a second branching point (I, OP10; P30, OP1, P42) connect said branching paths (BP40a, BP40b; BP50a, BP50b). The method comprises the steps of disconnecting each branching path (BP40a, BP40b; BP50a, BP50b) once at a time at a specific point in said at least one loop (40, 50; 60, 70, 80) which connects a driver to at least one specific receiving pin (P1-P19; P32-P42); calculating a delay value of a signal connection between said driver pin (P0; P30) and each of said receiving pin (P1-P19; P32-P42) for each of said disconnected branching paths (BP40a, BP40b, BP50a, BP50b) of each loop (40, 50; 60, 70, 80); storing maximum and/or minimum calculated delay values; and applying at least one of said delay values for static timing analysis of the electronic circuit.

    摘要翻译： 本发明涉及一种用于电子电路布线网的延迟计算方法，其中电子电路中的网包括驱动器引脚（P0; P30）和接收引脚（P1-P19; P32-P42） 一个环路（40,50,60,70,80），所述环路（40,50; 60,70,80）包括第一分支路径（BP40a，BP50a）和第二分支路径（BP40b，BP50b） 所述第一分支路径（BP40a，BP50a），其中至少第一和第二分支点（I，OP10; P30，OP1，P42）连接所述分支路径（BP40a，BP40b; BP50a，BP50b）。 该方法包括以下步骤：在将驱动器连接到所述至少一个回路（40,50,60,70,80）中的特定点处一次断开每个分支路径（BP40a，BP40b; BP50a，BP50b） 至少一个特定接收引脚（P1-P19; P32-P42）; 对于每个所述分离的分支路径（BP40a，BP40b，BP50a，BP50b），计算每个所述驱动器引脚（P0; P30）和每个所述接收引脚（P1-P19; P32-P42）之间的信号连接的延迟值 （40,50,60,70,80）; 存储最大和/或最小计算的延迟值; 以及对所述电子电路的静态时序分析应用所述延迟值中的至少一个。

    Write Buffer for Improved DRAM Write Access Patterns
    12.
    发明申请
    Write Buffer for Improved DRAM Write Access Patterns 失效
    写缓冲区，用于改进DRAM写访问模式

    公开(公告)号：US20110302367A1

    公开(公告)日：2011-12-08

    申请号：US12962774

    申请日：2010-12-08

    申请人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

    发明人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0804 ,  G06F12/0215 ,  G06F12/0897 ,  Y02D10/13

    摘要： The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

    摘要翻译： 本发明涉及用于操作DRAM主存储器的方法和相应的系统。 为多页提供一条缓冲线。 当向缓冲器写入数据时，根据其目的主存储器地址确定数据被写入哪个缓冲行。 存储由较低内存地址和数据组成的元组。 输入缓冲线的数据将按页进行排序，以防线路被刷新到主存储器。 对缓冲区条目进行排序会导致更少的页面打开和关闭，因为数据由存储器地址重新排列，因此以逻辑顺序排列。 通过对多个页面使用一行，只需要一个共同的组相关高速缓存的一部分存储器，从而显着地减少了开销。

    Signal Repowering Chip For 3-Dimensional Integrated Circuit
    13.
    发明申请
    Signal Repowering Chip For 3-Dimensional Integrated Circuit 失效
    3维集成电路信号重新加工芯片

    公开(公告)号：US20100237700A1

    公开(公告)日：2010-09-23

    申请号：US12754054

    申请日：2010-04-05

    申请人： Markus Buehler ,  Sebastian Ehrenreich ,  Juergen Koehl

    发明人： Markus Buehler ,  Sebastian Ehrenreich ,  Juergen Koehl

    IPC分类号： H05K1/02 ,  H01L27/06 ,  H01L21/66

    CPC分类号： G01R31/2889 ,  G01R31/318513 ,  H01L2924/0002 ,  Y10T307/492 ,  H01L2924/00

    摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

    摘要翻译： 一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。

    Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same
    14.
    发明申请
    Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same 有权
    用于集成电路物理设计过程的冗余微环结构的设计结构及其形成方法

    公开(公告)号：US20090158231A1

    公开(公告)日：2009-06-18

    申请号：US11955580

    申请日：2007-12-13

    申请人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

    摘要翻译： 一种用于集成电路的设计结构，该集成电路包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线，以及位于第一距离处的第四线 第二根电线在第二级线路上。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

    TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
    15.
    发明申请
    TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY 有权
    从图书馆创建的半导体产品的测试估计

    公开(公告)号：US20070099236A1

    公开(公告)日：2007-05-03

    申请号：US11163696

    申请日：2005-10-27

    申请人： Jeanne Bickford ,  Markus Buehler ,  Jason Hibbeler ,  Juergen Koehl

    发明人： Jeanne Bickford ,  Markus Buehler ,  Jason Hibbeler ,  Juergen Koehl

    IPC分类号： C40B30/02

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.

    摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT
    16.
    发明申请
    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 有权
    使用冗余路由增加VLSI布局的可靠性

    公开(公告)号：US20060265684A1

    公开(公告)日：2006-11-23

    申请号：US10908593

    申请日：2005-05-18

    申请人： Markus Buehler ,  John Cohn ,  David Hathaway ,  Jason Hibbeler ,  Juergen Koehl

    发明人： Markus Buehler ,  John Cohn ,  David Hathaway ,  Jason Hibbeler ,  Juergen Koehl

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5068

    摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

    摘要翻译： 公开了一种将冗余路径插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用交替 路线。 第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。 更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。 如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

    Signal repowering chip for 3-dimensional integrated circuit
    17.
    发明授权
    Signal repowering chip for 3-dimensional integrated circuit 失效
    三维集成电路信号重新加工芯片

    公开(公告)号：US08513663B2

    公开(公告)日：2013-08-20

    申请号：US12754054

    申请日：2010-04-05

    申请人： Markus Buehler ,  Sebastian Ehrenreich ,  Juergen Koehl

    发明人： Markus Buehler ,  Sebastian Ehrenreich ,  Juergen Koehl

    IPC分类号： H01L23/58 ,  H01L29/10

    CPC分类号： G01R31/2889 ,  G01R31/318513 ,  H01L2924/0002 ,  Y10T307/492 ,  H01L2924/00

    摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

    摘要翻译： 一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。

    POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS
    19.
    发明申请
    POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS 审中-公开
    用于集成电路的后路由耦合固定

    公开(公告)号：US20100257503A1

    公开(公告)日：2010-10-07

    申请号：US12417136

    申请日：2009-04-02

    申请人： Markus Buehler ,  Michael A. Kazda ,  Juergen Koehl

    发明人： Markus Buehler ,  Michael A. Kazda ,  Juergen Koehl

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for rerouting a wire in an integrated circuit includes determining a wire coupling a first circuit element to a second circuit element is experiencing capacitive coupling effects with one or more other wires; removing the wire from a netlist; dividing the structure into a routing grid; defining a first and second wire types; associating a penalty with each wire type; determining all possible paths through the routing grid between the first circuit element and the second circuit element; determining a weighted length for each path; and selecting the path having the lowest weighted length.

    摘要翻译： 一种用于在集成电路中重新布线的方法包括确定将第一电路元件连接到第二电路元件的线耦合正在经历与一个或多个其它线的电容耦合效应; 从网表中取出电线; 将结构划分为路由网格; 定义第一和第二线类型; 将罚款与每种电线类型相关联; 确定穿过所述第一电路元件和所述第二电路元件之间的路由网格的所有可能路径; 确定每个路径的加权长度; 并选择具有最低加权长度的路径。