公开(公告)号：US20080107149A1

公开(公告)日：2008-05-08

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01N25/72 ,  G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20070130551A1

公开(公告)日：2007-06-07

申请号：US11673369

申请日：2007-02-09

申请人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

发明人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

IPC分类号： G06F17/50

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US20070051875A1

公开(公告)日：2007-03-08

申请号：US11161941

申请日：2005-08-23

申请人： Fen Chen ,  Richard Kontra ,  Tom Lee ,  Theodore Levin ,  Christopher Muzzy ,  Timothy Sullivan

发明人： Fen Chen ,  Richard Kontra ,  Tom Lee ,  Theodore Levin ,  Christopher Muzzy ,  Timothy Sullivan

IPC分类号： H01J40/14 ,  H01L31/00

CPC分类号： G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

摘要： A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.

摘要翻译： 一种结构及其操作方法。 该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

公开(公告)号：US20070013072A1

公开(公告)日：2007-01-18

申请号：US11160468

申请日：2005-06-24

申请人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Sullivan ,  Steven Voldman

发明人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Sullivan ,  Steven Voldman

IPC分类号： H01L23/52

CPC分类号： H01L27/0248 ,  Y10S438/926

摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

摘要翻译： 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

公开(公告)号：US20060271910A1

公开(公告)日：2006-11-30

申请号：US11139816

申请日：2005-05-27

申请人： Aaron Burcham ,  Paul Harrington ,  C. Hodges ,  Rahul Kumar ,  James Lau ,  Timothy Sullivan ,  Jason Weber

发明人： Aaron Burcham ,  Paul Harrington ,  C. Hodges ,  Rahul Kumar ,  James Lau ,  Timothy Sullivan ,  Jason Weber

IPC分类号： G06F9/44

CPC分类号： G06F9/44505

摘要： Systems and methods for applying both profile and user customizations to an application user interface are provided. Profile customizations, created for a specialized use or field, are adapted to an application user interface, which has command-menu-toolbar contributions from various add-in modules. The user has access to the customizations through a user interface. Then, as a user is customizing the application, through commands, toolbars, and menus, the user customizations are tagged. A priority and group is assigned to each customization to allow for relative positioning of each customization. The difference between the user's final desired state and a reset state is computed. This difference computation is used to track the changes made to the application and to assist in resets of the customizations.

摘要翻译： 提供了将配置文件和用户定制应用于应用程序用户界面的系统和方法。 为专门用途或字段创建的配置文件自定义适用于具有各种加载项模块的命令菜单工具栏贡献的应用程序用户界面。 用户可以通过用户界面访问自定义。 然后，作为用户定制应用程序，通过命令，工具栏和菜单，用户自定义被标记。 优先级和组被分配给每个定制，以允许每个定制的相对定位。 计算用户的最终期望状态与复位状态之间的差异。 该差异计算用于跟踪对应用程序所做的更改，并协助重新设置自定义项。

公开(公告)号：US20060226142A1

公开(公告)日：2006-10-12

申请号：US11442911

申请日：2006-05-30

申请人： Jason Gill ,  David Harmon ,  Deborah Massey ,  Alvin Strong ,  Timothy Sullivan ,  Junichi Furukawa

发明人： Jason Gill ,  David Harmon ,  Deborah Massey ,  Alvin Strong ,  Timothy Sullivan ,  Junichi Furukawa

IPC分类号： H05B1/02

CPC分类号： G06F17/5077 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/0005 ,  H01L2924/00

摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

公开(公告)号：US20060212520A1

公开(公告)日：2006-09-21

申请号：US11080240

申请日：2005-03-15

申请人： Jay Logue ,  Timothy Sullivan ,  Richard Landsman ,  Phillip Goldman ,  Susan Goldman

发明人： Jay Logue ,  Timothy Sullivan ,  Richard Landsman ,  Phillip Goldman ,  Susan Goldman

IPC分类号： G06F15/16

CPC分类号： H04L63/0442 ,  H04L51/12 ,  H04L63/08 ,  H04L63/0807 ,  H04L63/0823 ,  H04L63/12

摘要： Systems and methods for allowing challenge messages to be sent directly to a recipient's inbox where normally the challenge message would be sent to a pending folder or deleted. Challenge messages sent between federated messaging services contain a federated token which can be identified, authenticated and validated to determine whether the challenge message should be sent to a recipient's inbox. The federated token can include an authentication portion and a validation portion. Authentication methods for the authentication portion can include, for example, checksums, salts, hashes and digital signatures. Once a federated token is authenticated by decrypting the authentication portion according to one or more of these authentication methods, the federated token is validated by determining the defined use-base and determining whether the receipt of the federated token satisfies the defined use.

公开(公告)号：US20060163685A1

公开(公告)日：2006-07-27

申请号：US10905905

申请日：2005-01-26

申请人： Fen Chen ,  Cathryn Christiansen ,  Richard Kontra ,  Tom Lee ,  Alvin Strong ,  Timothy Sullivan ,  Joseph Therrien

发明人： Fen Chen ,  Cathryn Christiansen ,  Richard Kontra ,  Tom Lee ,  Alvin Strong ,  Timothy Sullivan ,  Joseph Therrien

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

摘要翻译： 提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。 如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。 当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。 气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。 熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。 热机械应力还由于由其产生的气体引起的相变而收缩。 当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

公开(公告)号：US20060071676A1

公开(公告)日：2006-04-06

申请号：US10711418

申请日：2004-09-17

申请人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

发明人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 可以在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US20050098897A1

公开(公告)日：2005-05-12

申请号：US10702651

申请日：2003-11-07

申请人： Daniel Edelstein ,  Baozhen Li ,  Timothy Sullivan

发明人： Daniel Edelstein ,  Baozhen Li ,  Timothy Sullivan

IPC分类号： H01L23/532 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure for semiconductor integrated circuits is disclosed. The interconnection structure comprises a redundant layer, and at least one adhesion/diffusion barrier layer. The redundant layer comprises a metal or metal alloy selected from Ta, Mo, W, Be, Cr, Co, Ir, Ni, Nb, Os, Pd, Pt, Rb, Rh, Ru, and Th.

摘要翻译： 公开了一种用于半导体集成电路的互连结构。 互连结构包括冗余层和至少一个粘附/扩散阻挡层。 冗余层包括选自Ta，Mo，W，Be，Cr，Co，Ir，Ni，Nb，Os，Pd，Pt，Rb，Rh，Ru和Th中的金属或金属合金。