公开(公告)号：US06781212B1

公开(公告)日：2004-08-24

申请号：US09143585

申请日：1998-08-31

申请人： David Y. Kao ,  Rongsheng Yang

发明人： David Y. Kao ,  Rongsheng Yang

IPC分类号： H01L2900

CPC分类号： H01L21/823481 ,  H01L21/763 ,  H01L21/765

摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

摘要翻译： 提供了选择性掺杂沟槽隔离装置。 优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。 在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。 衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

公开(公告)号：US06316312B2

公开(公告)日：2001-11-13

申请号：US09730648

申请日：2000-12-05

申请人： Yauh-Ching Liu ,  David Y. Kao

发明人： Yauh-Ching Liu ,  David Y. Kao

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer. The invention also includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.

公开(公告)号：US5905280A

公开(公告)日：1999-05-18

申请号：US798241

申请日：1997-02-11

申请人： Yauh-Ching Liu ,  David Y. Kao

发明人： Yauh-Ching Liu ,  David Y. Kao

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L21/76895 ,  H01L28/84 ,  H01L28/90

摘要： The invention includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.

摘要翻译： 本发明包括一种结构，包括：a）延伸穿过绝缘层到达节点位置的开口; b）在开口内的导电间隔件，并使开口的至少一部分变窄; 导电间隔件具有内表面和外表面; c）与所述节点位置连接并沿着所述导电间隔物的内表面和外表面延伸的存储节点层，所述存储节点层和导电间隔物一起形成电容器存储节点; 以及d）可操作地接近存储节点的电介质层和电池板层。

公开(公告)号：US06958901B2

公开(公告)日：2005-10-25

申请号：US10853851

申请日：2004-05-25

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01L21/334 ,  H01L29/94 ,  H01G4/228

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

公开(公告)号：US06713348B2

公开(公告)日：2004-03-30

申请号：US10293124

申请日：2002-11-12

申请人： David Y. Kao ,  Li Li

发明人： David Y. Kao ,  Li Li

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

摘要翻译： 在形成半导体器件期间使用的方法包括以下步骤：在半导体衬底组件上形成多晶硅层，并在多晶硅层上形成氮化硅层。 在氮化硅层之上形成二氧化硅层，并且使用具有宽度的图案化掩模来对二氧化硅和氮化硅层进行图案化，从而在两层中形成侧壁。 氮化物层和氧化物层经受氧等离子体，其处理侧壁并且在未被处理的侧壁之间留下氮化硅层的一部分。 去除二氧化硅和氮化硅层的未处理部分，从而得到经处理的氮化硅的柱。 最后，使用柱作为掩模蚀刻多晶硅。 因此，图案化的多晶硅层包括具有比原始掩模的宽度窄的宽度的特征。

公开(公告)号：US6124173A

公开(公告)日：2000-09-26

申请号：US940309

申请日：1997-09-30

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating polarity. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：具有极性与空穴电荷极性相反的空间电荷的第一区域 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有极性与所述第一区域的空间电荷极性相反的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有极性与所述第二区域的空间电荷极性相反的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替极性的连续倾斜的植入物来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US6018175A

公开(公告)日：2000-01-25

申请号：US148032

申请日：1998-09-03

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01L21/334 ,  H01L29/94 ,  H01L27/108 ,  H01L29/00 ,  H01L29/76 ,  H01L29/93 ,  H01L31/119

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

公开(公告)号：US06602750B2

公开(公告)日：2003-08-05

申请号：US09996501

申请日：2001-11-27

申请人： David Y. Kao

发明人： David Y. Kao

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented. The second layer contacts the first layer to make electrical contact therewith and also defines a recess. A control gate is formed within the recess. Having the control gate formed in the floating gate layer recess increases the capacitive coupling between the floating and control gates thereby improving the electrical properties of the cell and allowing for a reduction in cell size while maintaining the coupling coefficient.

公开(公告)号：US06504211B1

公开(公告)日：2003-01-07

申请号：US09053352

申请日：1998-04-01

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L2701

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a charge opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a charge opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a charge opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating charge. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：第一区域，具有与空穴电荷相反的电荷的空间电荷 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有与所述第一区域的空间电荷相反的电荷的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有与所述第二区域的空间电荷相反的电荷的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替电荷的连续倾斜注入来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US06316326B1

公开(公告)日：2001-11-13

申请号：US09229857

申请日：1999-01-13

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01L2120

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semicondutor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

摘要翻译： 在半导体器件中，提供在其至少一个板上具有间隙的电容器。 间隙足够小，使得该间隙的侧面和相对的板之间的边缘电容至少补偿（如果不是过度补偿的）缺失的导电材料，否则将填充间隙并增加并联电容。 结果，可以增加存储装置的电容，而不占用更多的管芯面积。 或者，电容器的尺寸可以减小而不降低电容。 各种间隙配置和用于提供它们的方法也在本发明的范围内。