公开(公告)号：US06323514B1

公开(公告)日：2001-11-27

申请号：US09348725

申请日：1999-07-06

申请人： David Y. Kao

发明人： David Y. Kao

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented. The second layer contacts the first layer to make electrical contact therewith and also defines a recess. A control gate is formed within the recess. Having the control gate formed in the floating gate layer recess increases the capacitive coupling between the floating and control gates thereby improving the electrical properties of the cell and allowing for a reduction in cell size while maintaining

摘要翻译： 浮动栅极存储器件包括水平取向的第一导电浮动栅层和主要垂直取向的第二导电浮栅。 第二层接触第一层以与其电接触并且还限定凹部。 在凹槽内形成控制门。 使形成在浮栅层凹槽中的控制栅极增加了浮置栅极和控制栅极之间的电容耦合，从而提高了电池的电性能并且允许在保持电池尺寸的同时减小电池尺寸

公开(公告)号：US06144068A

公开(公告)日：2000-11-07

申请号：US277030

申请日：1999-03-25

申请人： David Y. Kao ,  Jeff Zhiqiang Wu

发明人： David Y. Kao ,  Jeff Zhiqiang Wu

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, A resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

摘要翻译： 一方面，一种在半导体衬底上形成晶体管器件的方法，包括：a）在衬底上形成晶体管栅极; b）形成与晶体管栅极可操作地相邻的第一极性源极有源区和第一极性漏极有源区; 以及c）形成第二极性内部结合区域，所述第二极性内部结合区域完全接收在所述第一极性区域之一内。 在另一方面，一种晶体管器件，包括：a）半导体衬底上的晶体管栅极; b）可操作地邻近晶体管栅极的第一极性源极有源区和第一极性漏极有源区; 以及c）完全接收在所述第一极性区域之一内的第二极性内部连接区域。 在另一方面，一种电阻器，包括：a）半导体衬底上的栅极，栅极由栅极电压供电; b）第一极性源有源区和可操作地邻近电动门的第一极性漏极有源区; c）完全接收在所述第一极性区域之一内的第二极性内部连接区域; 以及d）所述第一极性源极活性区域和所述第一极性漏极有源区域之间的电流，所述电流基本上线性地取决于所述漏极区域处的电压。

公开(公告)号：US6124167A

公开(公告)日：2000-09-26

申请号：US370064

申请日：1999-08-06

申请人： David Y. Kao ,  Li Li

发明人： David Y. Kao ,  Li Li

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

公开(公告)号：US07259442B2

公开(公告)日：2007-08-21

申请号：US10920579

申请日：2004-08-17

申请人： David Y. Kao ,  Rongsheng Yang

发明人： David Y. Kao ,  Rongsheng Yang

IPC分类号： H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/763 ,  H01L21/765

摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

摘要翻译： 提供了选择性掺杂沟槽隔离装置。 优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。 在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。 衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

公开(公告)号：US07151659B2

公开(公告)日：2006-12-19

申请号：US11038602

申请日：2005-01-18

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01G4/005

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

公开(公告)号：US06781212B1

公开(公告)日：2004-08-24

申请号：US09143585

申请日：1998-08-31

申请人： David Y. Kao ,  Rongsheng Yang

发明人： David Y. Kao ,  Rongsheng Yang

IPC分类号： H01L2900

CPC分类号： H01L21/823481 ,  H01L21/763 ,  H01L21/765

摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

摘要翻译： 提供了选择性掺杂沟槽隔离装置。 优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。 在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。 衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

公开(公告)号：US06316312B2

公开(公告)日：2001-11-13

申请号：US09730648

申请日：2000-12-05

申请人： Yauh-Ching Liu ,  David Y. Kao

发明人： Yauh-Ching Liu ,  David Y. Kao

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer. The invention also includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.

公开(公告)号：US5905280A

公开(公告)日：1999-05-18

申请号：US798241

申请日：1997-02-11

申请人： Yauh-Ching Liu ,  David Y. Kao

发明人： Yauh-Ching Liu ,  David Y. Kao

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L21/76895 ,  H01L28/84 ,  H01L28/90

摘要： The invention includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.

摘要翻译： 本发明包括一种结构，包括：a）延伸穿过绝缘层到达节点位置的开口; b）在开口内的导电间隔件，并使开口的至少一部分变窄; 导电间隔件具有内表面和外表面; c）与所述节点位置连接并沿着所述导电间隔物的内表面和外表面延伸的存储节点层，所述存储节点层和导电间隔物一起形成电容器存储节点; 以及d）可操作地接近存储节点的电介质层和电池板层。

公开(公告)号：US06958901B2

公开(公告)日：2005-10-25

申请号：US10853851

申请日：2004-05-25

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01L21/334 ,  H01L29/94 ,  H01G4/228

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

公开(公告)号：US06713348B2

公开(公告)日：2004-03-30

申请号：US10293124

申请日：2002-11-12

申请人： David Y. Kao ,  Li Li

发明人： David Y. Kao ,  Li Li

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

摘要翻译： 在形成半导体器件期间使用的方法包括以下步骤：在半导体衬底组件上形成多晶硅层，并在多晶硅层上形成氮化硅层。 在氮化硅层之上形成二氧化硅层，并且使用具有宽度的图案化掩模来对二氧化硅和氮化硅层进行图案化，从而在两层中形成侧壁。 氮化物层和氧化物层经受氧等离子体，其处理侧壁并且在未被处理的侧壁之间留下氮化硅层的一部分。 去除二氧化硅和氮化硅层的未处理部分，从而得到经处理的氮化硅的柱。 最后，使用柱作为掩模蚀刻多晶硅。 因此，图案化的多晶硅层包括具有比原始掩模的宽度窄的宽度的特征。