公开(公告)号：US6124173A

公开(公告)日：2000-09-26

申请号：US940309

申请日：1997-09-30

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating polarity. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：具有极性与空穴电荷极性相反的空间电荷的第一区域 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有极性与所述第一区域的空间电荷极性相反的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有极性与所述第二区域的空间电荷极性相反的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替极性的连续倾斜的植入物来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US06504211B1

公开(公告)日：2003-01-07

申请号：US09053352

申请日：1998-04-01

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L2701

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a charge opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a charge opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a charge opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating charge. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：第一区域，具有与空穴电荷相反的电荷的空间电荷 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有与所述第一区域的空间电荷相反的电荷的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有与所述第二区域的空间电荷相反的电荷的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替电荷的连续倾斜注入来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US06232190B1

公开(公告)日：2001-05-15

申请号：US09548418

申请日：2000-04-13

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L21336

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a charge opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a charge opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a charge opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating charge. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：第一区域，具有与空穴电荷相反的电荷的空间电荷 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有与所述第一区域的空间电荷相反的电荷的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有与所述第二区域的空间电荷相反的电荷的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替电荷的连续倾斜注入来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US5763916A

公开(公告)日：1998-06-09

申请号：US639903

申请日：1996-04-19

申请人： Fernando Gonzalez ,  David Y. Kao

发明人： Fernando Gonzalez ,  David Y. Kao

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating polarity. A storage node may then be formed above the third region.

摘要翻译： 一个MOS栅极和相关的源极/漏极区域结构，在源极/漏极接触区域和衬底之间提供三个结二极管，而不是典型的总共一个，从而改善了源/漏接触区域和存储节点的隔离， 在那里形成。 为了制造该结构，在其主体或主要部分中具有空间电荷的衬底中形成源极/漏极区域，源极/漏极区域包括：具有极性与空穴电荷极性相反的空间电荷的第一区域 在基材的主要部分; 第二区域，通过所述第一区域与所述衬底的主要部分分离并且具有极性与所述第一区域的空间电荷极性相反的空间电荷; 以及通过所述第二区域与所述第一区域和所述衬底的主要部分分离并且具有极性与所述第二区域的空间电荷极性相反的空间电荷的第三区域。 第一和第二区域横向延伸在相关门下。 第三区域横向延伸到栅极下方的区域的边界处，并且不延伸到栅极下方。 第三区域包括对应于源极/漏极接触区域的衬底表面的一部分。 源极/漏极区域可以通过交替极性的连续倾斜的植入物来制备。 然后可以在第三区域上方形成存储节点。

公开(公告)号：US06323514B1

公开(公告)日：2001-11-27

申请号：US09348725

申请日：1999-07-06

申请人： David Y. Kao

发明人： David Y. Kao

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented. The second layer contacts the first layer to make electrical contact therewith and also defines a recess. A control gate is formed within the recess. Having the control gate formed in the floating gate layer recess increases the capacitive coupling between the floating and control gates thereby improving the electrical properties of the cell and allowing for a reduction in cell size while maintaining

摘要翻译： 浮动栅极存储器件包括水平取向的第一导电浮动栅层和主要垂直取向的第二导电浮栅。 第二层接触第一层以与其电接触并且还限定凹部。 在凹槽内形成控制门。 使形成在浮栅层凹槽中的控制栅极增加了浮置栅极和控制栅极之间的电容耦合，从而提高了电池的电性能并且允许在保持电池尺寸的同时减小电池尺寸

公开(公告)号：US06144068A

公开(公告)日：2000-11-07

申请号：US277030

申请日：1999-03-25

申请人： David Y. Kao ,  Jeff Zhiqiang Wu

发明人： David Y. Kao ,  Jeff Zhiqiang Wu

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, A resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

摘要翻译： 一方面，一种在半导体衬底上形成晶体管器件的方法，包括：a）在衬底上形成晶体管栅极; b）形成与晶体管栅极可操作地相邻的第一极性源极有源区和第一极性漏极有源区; 以及c）形成第二极性内部结合区域，所述第二极性内部结合区域完全接收在所述第一极性区域之一内。 在另一方面，一种晶体管器件，包括：a）半导体衬底上的晶体管栅极; b）可操作地邻近晶体管栅极的第一极性源极有源区和第一极性漏极有源区; 以及c）完全接收在所述第一极性区域之一内的第二极性内部连接区域。 在另一方面，一种电阻器，包括：a）半导体衬底上的栅极，栅极由栅极电压供电; b）第一极性源有源区和可操作地邻近电动门的第一极性漏极有源区; c）完全接收在所述第一极性区域之一内的第二极性内部连接区域; 以及d）所述第一极性源极活性区域和所述第一极性漏极有源区域之间的电流，所述电流基本上线性地取决于所述漏极区域处的电压。

公开(公告)号：US6124167A

公开(公告)日：2000-09-26

申请号：US370064

申请日：1999-08-06

申请人： David Y. Kao ,  Li Li

发明人： David Y. Kao ,  Li Li

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

公开(公告)号：US07259442B2

公开(公告)日：2007-08-21

申请号：US10920579

申请日：2004-08-17

申请人： David Y. Kao ,  Rongsheng Yang

发明人： David Y. Kao ,  Rongsheng Yang

IPC分类号： H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/763 ,  H01L21/765

摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

摘要翻译： 提供了选择性掺杂沟槽隔离装置。 优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。 在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。 衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。

公开(公告)号：US07151659B2

公开(公告)日：2006-12-19

申请号：US11038602

申请日：2005-01-18

申请人： David Y. Kao ,  James Peacher

发明人： David Y. Kao ,  James Peacher

IPC分类号： H01G4/005

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L29/94

摘要： In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

公开(公告)号：US06781212B1

公开(公告)日：2004-08-24

申请号：US09143585

申请日：1998-08-31

申请人： David Y. Kao ,  Rongsheng Yang

发明人： David Y. Kao ,  Rongsheng Yang

IPC分类号： H01L2900

CPC分类号： H01L21/823481 ,  H01L21/763 ,  H01L21/765

摘要： A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

摘要翻译： 提供了选择性掺杂沟槽隔离装置。 优选实施例的沟槽隔离装置包括具有沟槽的半导体衬底。 在沟槽的侧壁上生长薄的氧化物层，并且沟槽被重掺杂的多晶硅填充。 衬底和重掺杂多晶硅之间的功函数差异增加了门控沟槽隔离器件的场阈值电压，使得可以在较高密度集成电路中的相邻有源器件之间形成更小的隔离结构。