公开(公告)号：US4500915A

公开(公告)日：1985-02-19

申请号：US423446

申请日：1982-09-24

申请人： Norio Koike ,  Toshihisa Tsukada ,  Toru Baji ,  Akira Sasano

发明人： Norio Koike ,  Toshihisa Tsukada ,  Toru Baji ,  Akira Sasano

IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L27/148 ,  H04N9/07

CPC分类号： H01L27/14843 ,  H01L27/14868 ,  H04N3/1575

摘要： The present invention consists in providing a CCD type color solid-state imager in which color signals respectively separated in time can be derived from picture elements for respective colors arrayed in the shape of a matrix and which permits interlacing without degrading a resolution and without causing image lag. Concretely, pairs of CCD shift registers which are electrically insulated and separated and which run in the vertical direction are arrayed in the horizontal direction, signal charges stored in adjacent picture elements are sent into the individual opposing CCD registers through transfer gates arrayed in a checkerboard pattern, and signal charges transferred in time sequence are distributed to a plurality of CCD shift registers which run in the horizontal direction, whereby a CCD type color solid-state imager having a high resolution and exhibiting no image lag is obtained.

摘要翻译： 本发明的目的在于提供一种CCD型彩色固态成像器，其中分别在时间上分离出的色信号可以从以矩阵形排列的各种颜色的图像元素中导出，并且允许隔行扫描而不降低分辨率并且不引起图像 落后。 具体地说，电绝缘和分离并沿垂直方向延伸的CCD对移位寄存器沿水平方向排列，存储在相邻像素中的信号电荷通过排列在棋盘图案中的传输门发送到各个相对的CCD寄存器 ，并且以时间顺序传送的信号电荷被分配到在水平方向上运行的多个CCD移位寄存器，由此获得具有高分辨率且不显示图像滞后的CCD型彩色固态成像器。

公开(公告)号：US4360821A

公开(公告)日：1982-11-23

申请号：US66230

申请日：1979-08-13

申请人： Toshihisa Tsukada ,  Eiichi Maruyama ,  Toru Baji ,  Saburo Ataka ,  Yoshinori Imamura ,  Akira Sasano ,  Masaharu Kubo ,  Norio Koike ,  Shusaku Nagahara

发明人： Toshihisa Tsukada ,  Eiichi Maruyama ,  Toru Baji ,  Saburo Ataka ,  Yoshinori Imamura ,  Akira Sasano ,  Masaharu Kubo ,  Norio Koike ,  Shusaku Nagahara

IPC分类号： H01L27/146 ,  H01L27/14

CPC分类号： H01L27/14665

摘要： In a solid-state imaging device having a plurality of photosensitive portions and a semiconductor substrate which includes at least scanning means for scanning the photosensitive portions, the photosensitive portions including a layer of a photosensitive material overlying the semiconductor substrate and a transparent electrically conductive film overlying the photosensitive material layer; a solid-state imaging device characterized in that the photosensitive material is an amorphous material whose indispensable constituent is silicon and which contains hydrogen. The hydrogen content of the photosensitive material is preferably 5 atomic-% to 30 atomic-%, especially 10 atomic-% to 25 atomic-%.

摘要翻译： 在具有多个感光部分的固态成像装置和至少包括用于扫描感光部分的扫描装置的半导体衬底上，感光部分包括覆盖在半导体衬底上的感光材料层和覆盖着透明导电膜的透明导电膜 感光材料层; 一种固态成像装置，其特征在于感光材料是不可缺少的成分是硅并且含有氢的无定形材料。 感光材料的氢含量优选为5原子％至30原子％，特别是10原子％至25原子％。

公开(公告)号：US06993597B2

公开(公告)日：2006-01-31

申请号：US10639445

申请日：2003-08-13

申请人： Tetsuya Nakagawa ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

发明人： Tetsuya Nakagawa ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

IPC分类号： G06F3/00

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F15/7807

摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

摘要翻译： 低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。 使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。 此外，DSP和CPU的数据输入和输出需要两个外设单元。 因此，DSP和CPU之间会发生无关的通信开销。 本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。 因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

公开(公告)号：US06434690B1

公开(公告)日：2002-08-13

申请号：US09229147

申请日：1999-01-11

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F1576

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

摘要翻译： 内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 因此，CPU核心2可以同时将两个数据值从内置存储器传送到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为 外部接口并且CPU核心2可以与访问第二存储器4和6以及第一存储器5和

公开(公告)号：US06405302B1

公开(公告)日：2002-06-11

申请号：US09291910

申请日：1999-04-14

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F1340

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US5832258A

公开(公告)日：1998-11-03

申请号：US364418

申请日：1994-12-27

申请人： Atsushi Kiuchi ,  Toru Baji

发明人： Atsushi Kiuchi ,  Toru Baji

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F9/3802 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/382

摘要： A digital signal processor that includes an execution unit, a condition code register, a program memory, a program control unit, and an instruction decoder. The program memory stores a sequence of instruction words and includes an instruction word that has at least one field that identifies a data processing operation to be performed by the execution unit. The instruction word also includes a condition code field that identifies a predefined condition and also identifies whether said condition code register should be updated when the data processing operation is performed by the execution unit. The program control unit outputs an instruction address to the program memory so as to select the instruction word in the program memory. The instruction decoder decodes the selected instruction word. It includes decoder circuitry for decoding the at least one field to generate control signals for controlling the execution unit to perform the specific data processing operation. The execution unit includes means for generating a current condition code flag if a corresponding predefined condition occurs when the execution unit performs the current data processing operation in response to the control signals. The instruction decoder further includes condition code decoder circuitry for decoding the condition code field to generate a control signal for enabling and disabling the condition code register to store the current condition code flag in accordance with the condition code field's value.

摘要翻译： 一种数字信号处理器，包括执行单元，条件码寄存器，程序存储器，程序控制单元和指令译码器。 程序存储器存储指令字序列，并且包括具有标识要由执行单元执行的数据处理操作的至少一个字段的指令字。 指令字还包括识别预定义条件的条件码字段，并且还识别当执行单元执行数据处理操作时是否应当更新所述条件码寄存器。 程序控制单元向程序存储器输出指令地址，以便选择程序存储器中的指令字。 指令译码器解码所选择的指令字。 它包括解码器电路，用于解码至少一个场以产生用于控制执行单元执行特定数据处理操作的控制信号。 执行单元包括当执行单元响应于控制信号执行当前数据处理操作而发生相应的预定条件时，生成当前条件码标志的装置。 指令解码器还包括条件码解码器电路，用于对条件代码字段进行解码，以产生用于根据条件代码字段的值来产生和禁用状态代码寄存器来存储当前条件代码标志的控制信号。

公开(公告)号：US20080207158A1

公开(公告)日：2008-08-28

申请号：US12112968

申请日：2008-04-30

申请人： Tetsuya NAKAGAWA ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

发明人： Tetsuya NAKAGAWA ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

IPC分类号： H04B1/26

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F15/7807

摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

摘要翻译： 低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。 使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。 此外，DSP和CPU的数据输入和输出需要两个外设单元。 因此，DSP和CPU之间会发生无关的通信开销。 本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。 因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

公开(公告)号：US07069423B2

公开(公告)日：2006-06-27

申请号：US10201402

申请日：2002-07-22

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F9/30

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US5426745A

公开(公告)日：1995-06-20

申请号：US206195

申请日：1994-03-03

申请人： Toru Baji ,  Kouki Noguchi ,  Tetsuya Nakagawa ,  Motonobu Tonomura ,  Hajime Akimoto ,  Toshiaki Masuhara

发明人： Toru Baji ,  Kouki Noguchi ,  Tetsuya Nakagawa ,  Motonobu Tonomura ,  Hajime Akimoto ,  Toshiaki Masuhara

IPC分类号： G06F15/18 ,  G06F3/00 ,  G06F3/16 ,  G06F15/00 ,  G06F15/02 ,  G06K9/52 ,  G06N3/00 ,  G06N99/00 ,  G07C9/00 ,  G10L15/06 ,  G10L15/16

CPC分类号： G10L15/16 ,  G06F3/16 ,  G06K9/522 ,  G07C9/00071 ,  G06K2209/01

摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

摘要翻译： 提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元 。 分别设置在语音，图像和指令识别单元中的至少两个中的神经网络，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音进行处理的处理器，以及通过识别识别的图像和指令 单位。 此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

公开(公告)号：US5027400A

公开(公告)日：1991-06-25

申请号：US394786

申请日：1989-08-16

申请人： Toru Baji ,  Yukio Nakano ,  Shiro Tanabe ,  Tetsuya Nakagawa ,  Hirotsugu Kojima

发明人： Toru Baji ,  Yukio Nakano ,  Shiro Tanabe ,  Tetsuya Nakagawa ,  Hirotsugu Kojima

IPC分类号： G06F17/30 ,  G09F27/00 ,  H04H9/00 ,  H04H20/28 ,  H04H20/76 ,  H04H60/31 ,  H04L12/00 ,  H04N7/16 ,  H04N7/173 ,  H04Q11/04

CPC分类号： H04H60/31 ,  G09F27/00 ,  H04H20/28 ,  H04H20/76 ,  H04N21/2543 ,  H04N21/4722 ,  H04N21/812 ,  H04N7/173 ,  H04N7/17336 ,  H04Q11/0478 ,  H04L2012/5638

摘要： A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscriber, a motion picture program data base, a commerical data base, a program transmitter for effecting accesses and transmissions of transmission programs onto transmission lines based on the setting of the main control unit, a commercial transmitter for accessing the commerical data base and for transmitting content thereof based on the setting of the main control unit, an image encoder for achieving a bandwidth compression on a video signal, a cell assembler for processing data to be transmitted onto a broadband transmission line so as to generate a cell of the data, and an asynchronous transfer mode exchange for delivering the cell to a subscriber system associated therewith. Each of the subscriber systems includes a network terminal, a terminal control unit, a decoder to decode the compressed video signal, and a television monitor.