公开(公告)号：US6015754A

公开(公告)日：2000-01-18

申请号：US996695

申请日：1997-12-23

申请人： Yasukazu Mase ,  Yoshitaka Matsui ,  Takeshi Kubota ,  Toshihiko Kitamura

发明人： Yasukazu Mase ,  Yoshitaka Matsui ,  Takeshi Kubota ,  Toshihiko Kitamura

IPC分类号： B24B37/013 ,  B24B49/10 ,  H01L21/304 ,  H01L21/321 ,  H01L21/302 ,  C23F1/02

CPC分类号： B24B37/005 ,  B24B49/10 ,  H01L21/32115

摘要： A CMP apparatus is used to subject a target surface of a semiconductor wafer to a polishing treatment, by moving the target surface and a polishing surface of a polishing cloth relative to each other while supplying a polishing liquid between the target surface and the polishing surface. Electric resistance is measured between pairs of measuring points arranged on opposite sides of dicing lines on the target surface, while subjecting the target surface to the polishing treatment. The polishing treatment is caused to be ended by comparing detected values of a changing rate in measured values of the electric property with a reference value set to correspond to an end point of the polishing treatment.

摘要翻译： CMP设备用于通过在目标表面和抛光表面之间提供抛光液体的同时相对于彼此移动目标表面和抛光布的抛光表面来对半导体晶片的目标表面进行抛光处理。 在目标表面上的切割线的相对侧的测量点对之间测量电阻，同时对目标表面进行抛光处理。 通过将电性能的测量值中的变化率的检测值与设置为对应于抛光处理的终点的参考值进行比较，结束抛光处理。

公开(公告)号：US5016663A

公开(公告)日：1991-05-21

申请号：US320643

申请日：1988-11-30

申请人： Yasukazu Mase ,  Masahiro Abe ,  Osamu Hirata

发明人： Yasukazu Mase ,  Masahiro Abe ,  Osamu Hirata

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065

CPC分类号： H01L21/67069 ,  H01L21/67011

摘要： In a method for determining an end of cleaning of a semiconductor manufacturing apparatus according to the invention, when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, a constant current or voltage is supplied from a high-frequency power source to discharge electrodes during plasma discharge, an impedance between the electrodes or a temperature in the process chamber is monitored, a time point at which the impedance or temperature is abruptly changed is detected, and this time point of detection is determined to be an end of cleaning.

摘要翻译： PCT No.PCT / JP88 / 00327 Sec。 371日期：1988年11月30日 102（e）1988年11月30日日期PCT提交1988年3月31日PCT公布。 公开号WO88 / 07757 日本10月6日，1988年。在根据本发明的用于确定半导体制造装置的清洁结束的方法中，当通过使用等离子体放电的干蚀刻来清洁半导体制造装置的半导体衬底处理室的内部时， 在等离子体放电期间从高频电源提供恒定电流或电压以放电电极，监测电极之间的阻抗或处理室中的温度，检测阻抗或温度突然变化的时间点， 并且该检测时间点被确定为清洁的结束。

公开(公告)号：US4952528A

公开(公告)日：1990-08-28

申请号：US416779

申请日：1989-10-04

申请人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura

发明人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76802 ,  H01L21/76819 ,  Y10S148/137

摘要： A method for manufacturing semiconductor devices comprising the steps of forming a first wiring pattern including first and second lower layers on a semiconductor body, forming an insulation film which covers the first wiring pattern, forming a first hole of 1.5 .mu.m and a second hole of 3 .mu.m in first and second areas of the insulation film which lie over the first and second lower layers, forming a second wiring pattern having first and second upper layers respectively connected to the first and second lower layers via the first and second holes. In the method, the hole formation step includes the substeps of forming a resist film which covers the insulation film, forming a resist pattern by effecting the photolithographic process of exposing the insulation film to light by using a mask pattern having a first hole defining area of 1.5 .mu.m and a second hole defining area of 2.4 .mu.m, and etching the insulation film with the resist pattern used as a mask. The exposing light amount used in the resist pattern formation substep is previously determined so that the size of the first hole can be set equal to that of the first hole defining area, and the reduced amount of the second hole defining area is previously determined so that the size of the second hole obtained under the determined exposing light amount can be set to 3 .mu.m.

公开(公告)号：US5411916A

公开(公告)日：1995-05-02

申请号：US77946

申请日：1993-03-18

申请人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

发明人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

IPC分类号： H01L21/3205 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L21/60

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14

摘要： As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

摘要翻译： 如图所示。 如图4所示，本发明的半导体集成电路器件的布线图形包括从连接孔延伸的布线部分和位于连接孔上的连接部分，并且在所述布线部分侧相对于所述连接孔具有匹配余量， 形成为比预定的宽度大的预定匹配余量，能够确保成功匹配所需的成品率。

公开(公告)号：US5169407A

公开(公告)日：1992-12-08

申请号：US623367

申请日：1990-12-07

申请人： Yasukazu Mase ,  Masahiro Abe ,  Osamu Hirata

发明人： Yasukazu Mase ,  Masahiro Abe ,  Osamu Hirata

IPC分类号： H01L21/00

CPC分类号： H01L21/67069 ,  H01L21/67011 ,  Y10T29/41

摘要： In a method for determining an end of cleaning of a semiconductor manufacturing apparatus according to the invention, when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, a constant current or voltage is supplied from a high-frequency power source to discharge electrodes during plasma discharge, an impedance between the electrodes or a temperature in the process chamber is monitored, a time point at which the impedance or temperature is abruptly changed is detected, and this time point of detection is determined to be an end of cleaning.

摘要翻译： 在根据本发明的用于确定半导体制造装置的清洁结束的方法中，当通过使用等离子体放电的干蚀刻来清洁半导体制造装置的半导体衬底处理室的内部时，从 在等离子体放电期间放电电极的高频电源，电极之间的阻抗或处理室中的温度被监测，检测到阻抗或温度突然改变的时间点，并且该检测时间点 决心结束清洁。

公开(公告)号：US5126819A

公开(公告)日：1992-06-30

申请号：US609601

申请日：1990-11-06

申请人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

发明人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

IPC分类号： H01L21/3205 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14

摘要： As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

公开(公告)号：US4857141A

公开(公告)日：1989-08-15

申请号：US181108

申请日：1988-04-13

申请人： Masahiro Abe ,  Yasukazu Mase

发明人： Masahiro Abe ,  Yasukazu Mase

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/768 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L21/76804 ,  H01L21/31116

摘要： A recess is formed in the surface area of a layer-insulation film by an isotropic etching process, and a hole is formed in the recess by a first anisotropic etching process. After this, a second anisotropic etching process is effected to taper the hole to remove an edge portion at the opening of the recess, the boundary portion between the recess and the side wall formed by the anisotropic etching process, and the vertical side wall of the hole. A wiring metal layer is formed on part of the layer-insulation film and in the hole.

公开(公告)号：US4728627A

公开(公告)日：1988-03-01

申请号：US870117

申请日：1986-06-03

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/00 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L21/76885 ,  H01L21/76877 ,  Y10S438/937

摘要： A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate on which a first insulation film is formed, forming a first conductive layer on the first insulation film, forming a hillock of the first conductive layer, forming a second insulation film on the structure, removing that portion of the second insulation film, in self-align with the hillock, which is on the hillock, thereby forming a contact hole leading to the first conductive layer, and forming on the structure a second conductive layer extending into the contact hole and contacting the first conductive layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备其上形成有第一绝缘膜的半导体衬底，在第一绝缘膜上形成第一导电层，形成第一导电层的小丘，在第一绝缘膜上形成第二绝缘膜 所述结构将所述第二绝缘膜的所述部分与所述小丘上的小丘自对准，从而形成通向所述第一导电层的接触孔，并且在所述结构上形成延伸到所述第一导电层的第二导电层 接触孔并与第一导电层接触。

公开(公告)号：US4613888A

公开(公告)日：1986-09-23

申请号：US634030

申请日：1984-07-24

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L23/532 ,  H01L21/44 ,  H01L21/47 ,  H01L21/94

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.

摘要翻译： 公开了一种半导体器件，其包括由作为绝缘夹层的硬质无机主绝缘膜和软嵌层膜形成的多层，以及作为最终钝化膜的硬质无机绝缘膜。 最终的钝化膜直接沉积在多层的硬质无机主绝缘膜上。