Nitride semiconductor device and method for fabricating the same
    11.
    发明授权
    Nitride semiconductor device and method for fabricating the same 有权
    氮化物半导体器件及其制造方法

    公开(公告)号:US07898002B2

    公开(公告)日:2011-03-01

    申请号:US11890480

    申请日:2007-08-07

    IPC分类号: H01L21/337 H01L21/335

    摘要: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

    摘要翻译: 氮化物半导体器件包括:衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

    EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI
    14.
    发明申请
    EXTERNAL DEVICE ACCESS APPARATUS, CONTROL METHOD THEREOF, AND SYSTEM LSI 审中-公开
    外部设备访问装置,其控制方法和系统LSI

    公开(公告)号:US20100318707A1

    公开(公告)日:2010-12-16

    申请号:US12866061

    申请日:2008-08-13

    IPC分类号: G06F13/24 G06F9/30

    摘要: An external device access apparatus according to the present invention includes: an address control unit that accepts a prefetch request and a prefetch data readout request from a master and performs a prefetch operation and a prefetch data readout operation; a readout data storage unit that stores data read out through the prefetch operation; a storage operation status holding unit that holds a prefetch operation status indicating whether or not the prefetch operation has been completed; and an acceptance signal generation unit that outputs, to the master, an acceptance signal indicating that the prefetch data readout request has been accepted from the master. First information indicating a status of the prefetch operation is outputted to the master based on the prefetch operation status.

    摘要翻译: 根据本发明的外部设备接入装置包括:地址控制单元,其从主机接收预取请求和预取数据读出请求,并执行预取操作和预取数据读出操作; 读出数据存储单元,存储通过预取操作读出的数据; 存储操作状态保持单元,其保存指示预取操作是否已经完成的预取操作状态; 以及接收信号生成单元,其向主设备输出表示预取数据读出请求已经从主机接受的接收信号。 基于预取操作状态,将指示预取操作的状态的第一信息输出到主机。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    17.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20100244045A1

    公开(公告)日:2010-09-30

    申请号:US12795143

    申请日:2010-06-07

    IPC分类号: H01L29/20

    摘要: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

    摘要翻译: 半导体器件包括形成在衬底上的第一半导体层,形成在第一半导体层上彼此间隔开的肖特基电极和欧姆电极以及形成为覆盖第一半导体层的第二半导体层 肖特基电极和欧姆电极暴露。 第二半导体层具有比第一半导体层更大的带隙。

    Semiconductor device including independent active layers and method for fabricating the same
    18.
    发明授权
    Semiconductor device including independent active layers and method for fabricating the same 有权
    包括独立有源层的半导体器件及其制造方法

    公开(公告)号:US07800097B2

    公开(公告)日:2010-09-21

    申请号:US11299818

    申请日:2005-12-13

    摘要: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.

    摘要翻译: 半导体器件包括n型硅的半导体衬底,在其上部包括彼此间隔开并掺杂有p型杂质的第一极性反转区域和第二极性反转区域。 包括第一有源层的第一HFET和包括由III-V族氮化物半导体构成的第二有源层的第二HFET独立地形成在半导体衬底中的相应极性反转区域上,并且HFET彼此电连接 通过互连。

    HERMETIC SEALING CAP, ELECTRONIC COMPONENT ACCOMMODATION PACKAGE, AND METHOD FOR PRODUCING HERMETIC SEALING CAP
    20.
    发明申请
    HERMETIC SEALING CAP, ELECTRONIC COMPONENT ACCOMMODATION PACKAGE, AND METHOD FOR PRODUCING HERMETIC SEALING CAP 有权
    密封密封盖,电子元件住宿包装及生产密封密封垫的方法

    公开(公告)号:US20090301749A1

    公开(公告)日:2009-12-10

    申请号:US11915914

    申请日:2007-02-13

    IPC分类号: H05K5/06 B44C1/22 B23K1/20

    摘要: A hermetic sealing cap can be provided which is capable of suppressing that a production process becomes complicated, and additionally of suppressing that a solder layer wetly spreads inward on a sealing surface. This hermetic sealing cap (1, 30) includes a base member (2), a first plating layer (3, 31) that is formed on the surface of the base member, and a second plating layer (4, 32) that is formed on the surface of the first plating layer and is less oxidized than the first plating layer, wherein a part of the second plating layer in an area (S1, S5) inside an area (S2, S6) to which an electronic component accommodation member is joined is removed so that the surface of the first plating layer is exposed, and the surface of the first plating layer that is exposed in the area from which the second plating layer is removed is oxidized.

    摘要翻译: 可以提供一种能够抑制生产过程变得复杂的气密密封盖,另外抑制焊料层在密封表面上向内湿润地扩展。 该气密密封盖(1,30)包括基体(2),形成在基体表面上的第一镀层(3,31)和形成的第二镀层(4,32) 在第一镀层的表面上比第一镀层氧化少,其中在电子部件容纳部件的区域(S2,S6)内的区域(S1,S5)内的区域(S1,S5)中的部分第二镀层 被除去,使得第一镀层的表面被暴露,并且暴露在从其去除第二镀层的区域中的第一镀层的表面被氧化。