公开(公告)号：US5146308A

公开(公告)日：1992-09-08

申请号：US593177

申请日：1990-10-05

申请人： Randal W. Chance ,  Eugene H. Cloud

发明人： Randal W. Chance ,  Eugene H. Cloud

IPC分类号： H01L23/485 ,  H01L25/065

CPC分类号： H01L24/02 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.

摘要翻译： 半导体管芯上的管芯接合位置沿着管芯的边缘形成为垂直插入件。 垂直插入件与基板隔离，并通过晶片锯工艺进行曝光，其中将晶片从晶片上分离出来。 该配置提供了更有效的布局的优点，允许模具的整个顶表面被钝化，更好的接触配置和用于包装的更方便的组装。

公开(公告)号：US07767129B2

公开(公告)日：2010-08-03

申请号：US11127942

申请日：2005-05-11

申请人： Gurtej S. Sandhu ,  Randal W. Chance

发明人： Gurtej S. Sandhu ,  Randal W. Chance

IPC分类号： B24B33/055 ,  B29C59/00 ,  H01L27/00

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  Y10S977/887 ,  Y10T428/249921

摘要： The invention comprises methods of patterning a plurality of substrates, and imprint templates used in imprint lithography. In one implementation, a method of patterning a plurality of substrates includes providing an imprint template having a plurality of spaced features. A first substrate is imprinted with the imprint template effective to form a plurality of recesses into the first substrate from the spaced features. After imprinting the first substrate, an elevationally outermost portion of the spaced features is removed effective to reduce elevation of the spaced features. After the removing, a second substrate is imprinted with the imprint template using the elevation-reduced spaced features effective to form a plurality of recesses into the second substrate from the elevation-reduced spaced features. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括图案化多个基板的方法，以及在压印光刻中使用的压印模板。 在一个实现中，图案化多个基板的方法包括提供具有多个间隔特征的印模模板。 第一衬底被印有压印模板，有效地从间隔的特征形成到第一衬底中的多个凹部。 在压印第一基板之后，去除间隔特征的高度最外部的部分，以有效地减少间隔的特征的高度。 在移除之后，使用升降间隔的特征，用压印模板压印第二基板，其有效地从升降间隔的特征形成到第二基板中的多个凹部。 考虑了其他方面和实现。

公开(公告)号：US07435536B2

公开(公告)日：2008-10-14

申请号：US11472130

申请日：2006-06-20

申请人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

IPC分类号： G03F7/26 ,  G03F7/00

CPC分类号： H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

公开(公告)号：US07271413B2

公开(公告)日：2007-09-18

申请号：US11274727

申请日：2005-11-14

申请人： Randal W. Chance ,  Gordon A. Haller ,  Sanh D. Tang ,  Steven D. Cummings

发明人： Randal W. Chance ,  Gordon A. Haller ,  Sanh D. Tang ,  Steven D. Cummings

IPC分类号： H01L27/108

CPC分类号： H01L29/66666 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/7827

摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

摘要翻译： 本发明包括包含垂直延伸柱的半导体结构以及用于形成这种结构的方法。 垂直延伸的柱可以并入晶体管器件中，并且可以包含晶体管器件的垂直延伸的沟道区域。 晶体管器件可以并入到集成电路中，并且在一些方面被并入存储器结构中，例如动态随机存取存储器（DRAM）结构。

公开(公告)号：US07122425B2

公开(公告)日：2006-10-17

申请号：US10925789

申请日：2004-08-24

申请人： Randal W. Chance ,  Gordon A. Haller ,  Sanh D. Tang ,  Steven D. Cummings

发明人： Randal W. Chance ,  Gordon A. Haller ,  Sanh D. Tang ,  Steven D. Cummings

IPC分类号： H01L21/8242

CPC分类号： H01L29/66666 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/7827

摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

公开(公告)号：US5126286A

公开(公告)日：1992-06-30

申请号：US593155

申请日：1990-10-05

申请人： Randal W. Chance

发明人： Randal W. Chance

IPC分类号： H01L23/485

CPC分类号： H01L25/0657 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2225/06551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.

摘要翻译： 半导体管芯上的管芯接合位置沿着管芯的边缘形成为垂直插入件。 垂直插入件与基板隔离，并通过晶片锯工艺进行曝光，其中将晶片从晶片上分离出来。 该配置提供了更有效的布局的优点，允许模具的整个顶表面被钝化，更好的接触配置和用于包装的更方便的组装。