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    Through silicon via (TSV) process
    11.
    发明授权
    Through silicon via (TSV) process 有权
    通过硅通孔（TSV）工艺

    公开(公告)号：US09412653B2

    公开(公告)日：2016-08-09

    申请号：US14817227

    申请日：2015-08-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

    IPC: H01L21/44 ,  H01L21/768

    CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

    Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

    Method for forming patterns
    12.
    发明授权
    Method for forming patterns 有权
    形成图案的方法

    公开(公告)号：US09316901B2

    公开(公告)日：2016-04-19

    申请号：US14259173

    申请日：2014-04-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

    IPC: G03F9/00 ,  G03F1/36 ,  G03F1/70 ,  G03F1/68

    CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

    Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.

    Abstract translation: 形成图案的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一布局。 提供包括第二目标图案和第二可打印虚拟图案的第二布局，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚设图案不能形成在晶片中。

    Method of fabricating a semiconductor device with fin-shaped structures
    13.
    发明授权
    Method of fabricating a semiconductor device with fin-shaped structures 有权
    制造具有鳍状结构的半导体器件的方法

    公开(公告)号：US09281400B1

    公开(公告)日：2016-03-08

    申请号：US14726620

    申请日：2015-06-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Hao-Ming Lee ,  Tzyy-Ming Cheng

    IPC: H01L21/339 ,  H01L29/78 ,  H01L21/8234

    CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/8258

    Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

    Abstract translation: 制造具有鳍状结构的半导体器件的方法包括分别在半导体衬底的第一区域和第二区域中形成第一鳍状结构，沉积介电层以完全覆盖第一鳍状结构，去除第一 在第二区域中形成鳍状结构，以便在电介质层中形成沟槽，并且进行原位掺杂外延生长工艺以在沟槽中分别形成第二鳍状结构。

    Through silicon via and method of forming the same
    14.
    发明授权
    Through silicon via and method of forming the same 有权
    通过硅通孔及其形成方法

    公开(公告)号：US08841755B2

    公开(公告)日：2014-09-23

    申请号：US13947125

    申请日：2013-07-22

    Applicant: United Microelectronics Corp.

    Inventor： Kuo-Hsiung Huang ,  Chun-Mao Chiou ,  Hsin-Yu Chen ,  Yu-Han Tsai ,  Ching-Li Yang ,  Home-Been Cheng

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/525

    CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

    Abstract translation: 本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。 绝缘层设置在通孔开口的表面上。 阻挡层设置在绝缘层的表面上。 缓冲层设置在阻挡层的表面上。 导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。 缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    15.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250063776A1

    公开(公告)日：2025-02-20

    申请号：US18373953

    申请日：2023-09-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Chen ,  Chun-Hao Lin ,  Yuan-Ting Chuang ,  Shou-Wei Hsieh

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.

    SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210210628A1

    公开(公告)日：2021-07-08

    申请号：US17207751

    申请日：2021-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

    IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

    Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    19.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190043964A1

    公开(公告)日：2019-02-07

    申请号：US15690260

    申请日：2017-08-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

    IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/06

    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; removing the second gate structure and part of the fin-shaped structure to forma first trench; forming a dielectric layer into the first trench; and planarizing part of the dielectric layer to form a single diffusion break (SDB) structure. Preferably, the top surfaces of the SDB structure and the first gate structure are coplanar.

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