公开(公告)号：US20170323950A1

公开(公告)日：2017-11-09

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US20160336270A1

公开(公告)日：2016-11-17

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract translation: 用于形成插头的半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成钛层以保形地覆盖凹部。 第一氮化钛层被形成为保形地覆盖钛层，由此第一氮化钛层具有第一侧壁部分。 第一氮化钛层的第一侧壁部分被拉回，从而形成第二侧壁部分。 形成第二氮化钛层以覆盖凹部。 此外，还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20250159916A1

公开(公告)日：2025-05-15

申请号：US19019409

申请日：2025-01-13

Applicant: UNITED MICROELECTRONICS CORP,

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H10D30/01 ,  H01L21/324 ,  H01L21/768 ,  H10D30/47 ,  H10D62/85

Abstract: A high electron mobility transistor includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, a gate structure disposed on the barrier layer, a source contact structure and a drain contact structure disposed on the barrier layer at two sides of the gate structure, and extending through the barrier layer to directly contact the channel layer, and a gate contact structure disposed on the gate structure. The source contact structure, the drain contact structure, and the gate contact structure respectively include a liner and a metal layer directly disposed on the liner. The metal layer comprises a metal material doped with a first additive, and a weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US12058851B2

公开(公告)日：2024-08-06

申请号：US18199346

申请日：2023-05-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L21/48 ,  H01L21/768 ,  H10B12/00

CPC classification number: H10B12/485 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76895 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US11222784B2

公开(公告)日：2022-01-11

申请号：US16831827

申请日：2020-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

公开(公告)号：US20210151442A1

公开(公告)日：2021-05-20

申请号：US17161685

申请日：2021-01-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/768

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US20200227264A1

公开(公告)日：2020-07-16

申请号：US16831827

申请日：2020-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

公开(公告)号：US10374051B1

公开(公告)日：2019-08-06

申请号：US15987891

申请日：2018-05-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ji-Min Lin ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Yi-An Huang ,  Kai-Jiun Chang

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/43

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US09985110B2

公开(公告)日：2018-05-29

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09640482B1

公开(公告)日：2017-05-02

申请号：US15097301

申请日：2016-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Min-Chuan Tsai ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Kuo-Chin Hung ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266

Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.