公开(公告)号：US20150357430A1

公开(公告)日：2015-12-10

申请号：US14324092

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/51 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成堆叠结构; 图案化堆叠结构以在界面层上形成栅极结构; 在界面层和栅极结构上形成衬垫; 以及去除衬套的一部分和用于形成间隔物的界面层的一部分。

公开(公告)号：US12261052B2

公开(公告)日：2025-03-25

申请号：US18608940

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H10D30/01 ,  H01L21/306 ,  H01L21/308 ,  H10D30/47 ,  H10D62/824 ,  H10D62/85

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US20250014941A1

公开(公告)日：2025-01-09

申请号：US18227991

申请日：2023-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yuan Wen ,  Lung-En Kuo ,  Chung-Yi Chiu

IPC: H01L21/762

Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.

公开(公告)号：US20240379670A1

公开(公告)日：2024-11-14

申请号：US18206609

申请日：2023-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Hu ,  Chih-Yi Wang ,  Yao-Jhan Wang ,  Wei-Che Chen ,  Kun-Szu Tseng ,  Yun-Yang He ,  Wen-Liang Huang ,  Lung-En Kuo ,  Po-Tsang Chen ,  Po-Chang Lin ,  Ying-Hsien Chen

IPC: H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

公开(公告)号：US11881409B2

公开(公告)日：2024-01-23

申请号：US17359669

申请日：2021-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hao Huang ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chia-Wei Hsu

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/027 ,  G03F1/38

CPC classification number: H01L21/3085 ,  H01L21/0274 ,  H01L21/30604 ,  G03F1/38

Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

公开(公告)号：US20250098238A1

公开(公告)日：2025-03-20

申请号：US18383035

申请日：2023-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Tien-Shan Hsu ,  Po-Chang Lin ,  Lung-En Kuo ,  Hao-Che Feng ,  Ping-Wei Huang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

公开(公告)号：US20240222133A1

公开(公告)日：2024-07-04

申请号：US18608940

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/3086 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/3085 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US09711368B2

公开(公告)日：2017-07-18

申请号：US13862484

申请日：2013-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/308 ,  H01L21/66 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823821 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L29/66795 ,  H01L29/785

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

公开(公告)号：US20160043195A1

公开(公告)日：2016-02-11

申请号：US14919738

申请日：2015-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底，衬底上的栅极结构和与栅极结构相邻的间隔物，其中间隔物的底部包括锥形轮廓，并且锥形轮廓包括凸曲线。

公开(公告)号：US09117909B2

公开(公告)日：2015-08-25

申请号：US14470957

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。