公开(公告)号：US20170062339A1

公开(公告)日：2017-03-02

申请号：US14856573

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L21/823475 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug adjacent to the first gate structure and contact the first spacer, and a first overhang feature disposed on an upper end of the first spacer.

Abstract translation: 半导体器件包括衬底，衬底上的第一栅极结构，与第一栅极结构相邻的第一间隔物，与第一栅极结构相邻并接触第一间隔物的下部接触插塞以及设置在上部的第一突出特征 第一间隔物的末端。

公开(公告)号：US10283412B2

公开(公告)日：2019-05-07

申请号：US15697462

申请日：2017-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/28 ,  H01L23/485 ,  H01L23/532

Abstract: A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.

公开(公告)号：US09922974B2

公开(公告)日：2018-03-20

申请号：US15641336

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L21/8234 ,  H01L23/485

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20160336270A1

公开(公告)日：2016-11-17

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract translation: 用于形成插头的半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成钛层以保形地覆盖凹部。 第一氮化钛层被形成为保形地覆盖钛层，由此第一氮化钛层具有第一侧壁部分。 第一氮化钛层的第一侧壁部分被拉回，从而形成第二侧壁部分。 形成第二氮化钛层以覆盖凹部。 此外，还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20140248762A1

公开(公告)日：2014-09-04

申请号：US14277812

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Nien-Ting Ho ,  Bor-Shyang Liao ,  Shu Min Huang ,  Min-Chung Cheng ,  Yu-Ru Yang

IPC: H01L21/768

CPC classification number: H01L21/76889 ,  H01L29/41791 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 首先，提供基板，在基板上形成至少一个翅片结构，然后在翅片结构上沉积金属层以形成自对准硅化物层。 在沉积金属层之后，除去金属层，但在除去金属层之前不进行RTP。 然后在去除金属层之后执行RTP。

公开(公告)号：US10068797B2

公开(公告)日：2018-09-04

申请号：US15586240

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US09230816B1

公开(公告)日：2016-01-05

申请号：US14629502

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/324 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L21/3081 ,  H01L21/32053 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成介电层; 在介电层上形成图案化的硬掩模; 在介电层和ILD层中形成开口; 执行在开口中形成硅化物层的硅化物工艺; 在硅化物处理后去除图案化的硬掩模和未反应的金属; 并在开口中形成接触塞。

公开(公告)号：US08993390B2

公开(公告)日：2015-03-31

申请号：US14277812

申请日：2014-05-15

Applicant: United Microelectronics Corp.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Nien-Ting Ho ,  Bor-Shyang Liao ,  Shu Min Huang ,  Min-Chung Cheng ,  Yu-Ru Yang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76889 ,  H01L29/41791 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 首先，提供基板，在基板上形成至少一个翅片结构，然后在翅片结构上沉积金属层以形成自对准硅化物层。 在沉积金属层之后，除去金属层，但在除去金属层之前不进行RTP。 然后在去除金属层之后执行RTP。

公开(公告)号：US08877635B2

公开(公告)日：2014-11-04

申请号：US13913535

申请日：2013-06-10

Applicant: United Microelectronics Corp.

Inventor： Kuo-Chih Lai ,  Nien-Ting Ho ,  Shu Min Huang ,  Bor-Shyang Liao ,  Chia Chang Hsu

IPC: H01L21/44 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324

CPC classification number: H01L21/324 ,  H01L21/02068 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.

Abstract translation: 公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。 该方法包括以下步骤：提供其上具有硅化物的半导体衬底; 执行第一快速热处理以将铂从硅化物的表面驱入硅化物; 并在第一快速热处理中除去未反应的铂。

公开(公告)号：US20140242802A1

公开(公告)日：2014-08-28

申请号：US13775273

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Kuo-Chih Lai ,  Chun-Ling Lin ,  Bor-Shyang Liao ,  Pin-Hong Chen ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/02

CPC classification number: H01L21/02063 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/76804 ,  H01L21/76814

Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.

Abstract translation: 半导体工艺包括以下步骤。 提供了基座上的晶片。 将基座抬起以接近加热源，并对晶片进行蚀刻处理。 通过加热源对晶片进行退火处理。 另一方面，提供了基座上的晶片和与基座在晶片相同侧的加热源。 通过将加热源和基座之间的温差设定为大于180℃，对晶片进行蚀刻处理。