公开(公告)号：US09666507B2

公开(公告)日：2017-05-30

申请号：US14556215

申请日：2014-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chien-Li Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through-substrate structure is disclosed. The method includes the steps of: providing a substrate; forming a through-substrate hole and a through-substrate trench in the substrate; and forming a metal layer in the through-substrate hole and the through-substrate trench for forming a through-substrate via and a through-substrate conductor having a void therein.

公开(公告)号：US09343359B2

公开(公告)日：2016-05-17

申请号：US14140523

申请日：2013-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L21/76879 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract translation: 公开了一种制造一体化结构的方法。 该方法包括以下步骤：提供衬底; 在所述基板中形成贯通硅孔; 在衬底上形成图案化的抗蚀剂，其中所述图案化抗蚀剂包括对应于再分布层（RDL）图案的至少一个开口，并暴露所述穿硅孔和至少另一个对应于另一再分布层（RDL）图案的开口，并连接到 所述至少一个开口; 以及形成导电层以填充图案化的抗蚀剂中的通孔，至少一个开口和至少另一个开口，以便形成贯穿硅通孔，穿硅通孔RDL图案和另一RDL图案 一个结构。

公开(公告)号：US11646343B2

公开(公告)日：2023-05-09

申请号：US17136075

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A capacitor structure comprises a substrate having a first side and a second side opposite to the first side; a plurality of first trenches formed on the first side of the substrate; a plurality of second trenches formed on the second side of the substrate; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

公开(公告)号：US20210005559A1

公开(公告)日：2021-01-07

申请号：US17023967

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US10790248B2

公开(公告)日：2020-09-29

申请号：US16280938

申请日：2019-02-20

Applicant: United Microelectronics Corp.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Provided are a three-dimensional integrated circuit (3DIC) and a method of manufacturing the same. The 3DIC includes a first wafer, a second wafer, and a hybrid bonding structure. The second wafer is bonded to the first wafer by the hybrid bonding structure. The hybrid bonding structure includes a blocking layer between a hybrid bonding dielectric layer and a hybrid bonding metal layer.

公开(公告)号：US10192808B1

公开(公告)日：2019-01-29

申请号：US15642349

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Ming-Tse Lin

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/321

Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.

公开(公告)号：US20150179516A1

公开(公告)日：2015-06-25

申请号：US14140523

申请日：2013-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract translation: 公开了一种制造一体化结构的方法。 该方法包括以下步骤：提供衬底; 在所述基板中形成贯通硅孔; 在衬底上形成图案化的抗蚀剂，其中所述图案化抗蚀剂包括对应于再分布层（RDL）图案的至少一个开口，并暴露所述穿硅孔和至少另一个对应于另一再分布层（RDL）图案的开口，并连接到 所述至少一个开口; 以及形成导电层以填充图案化的抗蚀剂中的通孔，至少一个开口和至少另一个开口，以便形成贯穿硅通孔，穿硅通孔RDL图案和另一RDL图案 一个结构。

公开(公告)号：US20140346645A1

公开(公告)日：2014-11-27

申请号：US13900565

申请日：2013-05-23

Applicant: United Microelectronics Corp.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Abstract translation: 透硅通孔包括基底和导电塞。 基板在一侧具有孔。 导电插头设置在孔中，导电插头具有从侧面突出的上部，其中上部具有顶部和底部，并且顶部比底部更细。 此外，还提供了通过硅通孔形成的贯穿硅通孔工艺，其包括以下步骤。 从一侧在基板上形成孔。 形成第一导电材料以覆盖孔和侧面。 形成图案化的光致抗蚀剂以覆盖侧面但暴露孔。 在暴露的第一导电材料上形成第二导电材料。 去除图案化的光致抗蚀剂。 去除侧面上的第一导电材料以在孔中形成导电塞。

公开(公告)号：US12034038B2

公开(公告)日：2024-07-09

申请号：US18119043

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/91

Abstract: A method for manufacturing a capacitor structure is provided. A substrate having a first side and a second side opposite to the first side is provided. A plurality of first trenches are formed on the first side. A first capacitor is formed extending along the first side and into the first trenches. A plurality of second trenches are formed on the second side. A second capacitor is formed extending along the second side and into the second trenches.

公开(公告)号：US11699646B2

公开(公告)日：2023-07-11

申请号：US17943215

申请日：2022-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L27/08 ,  H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/48 ,  H01L27/01 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L27/01 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16113 ,  H01L2224/16147

Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.