公开(公告)号：US10373829B1

公开(公告)日：2019-08-06

申请号：US16052625

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yin Hsieh ,  Chih-Sheng Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: A patterning method includes the following steps. A layout pattern is provided to a computer system. The layout pattern includes stripe patterns, and each of the stripe patterns extends in a first direction. Mandrel patterns are formed corresponding to a part of the stripe patterns. Each of the mandrel patterns extends in the first direction. A modification is performed to the mandrel patterns for elongating at least a part of the mandrel patterns in the first direction. Ends of the mandrel patterns in the first direction are aligned in a second direction perpendicular to the first direction after the modification. The mandrel patterns are outputted to a photomask after the modification. A photolithography process using the photomask is performed for forming a patterned structure on a substrate. By performing the modification to the mandrel patterns, design flexibility of the layout pattern corresponding to the patterning method may be enhanced.

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20170069529A1

公开(公告)日：2017-03-09

申请号：US15356677

申请日：2016-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Hao Fu ,  Home-Been Cheng ,  Ci-Dong Chu ,  Tsung-Yin Hsieh

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76877

Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate including a hard mask layer and a sacrificial layer is provided. A plurality of mandrel patterns are formed on the substrate. A spacer is respectively formed on sidewalls of the mandrel patterns. The mandrel patterns are removed to form a plurality of spacer patterns directly formed on the sacrificial layer. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion of the first blocking layers are formed on the substrate. The sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers, and the second blocking layers serving as etching masks to form a patterned hard mask layer on the substrate.

Abstract translation: 用于形成半导体器件的图案的方法包括以下步骤。 提供了包括硬掩模层和牺牲层的基板。 在基板上形成多个心轴图案。 间隔件分别形成在心轴图案的侧壁上。 去除心轴图案以形成直接形成在牺牲层上的多个间隔图案。 在形成间隔物图案之后，在牺牲层中形成多个第一阻挡层。 在衬底上形成暴露至少一部分牺牲层和至少一部分第一阻挡层的多个第二阻挡层。 用间隔物图案，第一阻挡层和第二阻挡层用作蚀刻掩模来蚀刻牺牲层和硬掩模层，以在衬底上形成图案化的硬掩模层。

公开(公告)号：US09536751B2

公开(公告)日：2017-01-03

申请号：US14741426

申请日：2015-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Hao Fu ,  Home-Been Cheng ,  Ci-Dong Chu ,  Tsung-Yin Hsieh

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76877

Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate is provided. The substrate includes a hard mask layer and a sacrificial layer formed thereon. A plurality of spacer patterns parallel with each other are formed on the substrate. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion the first blocking layer are formed on the substrate after forming the first blocking layer. Next, the sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers and the second blocking layer being used as etching masks to form a patterned hard mask layer on the substrate.

Abstract translation: 用于形成半导体器件的图案的方法包括以下步骤。 提供基板。 基板包括硬掩模层和形成在其上的牺牲层。 在基板上形成有彼此平行的多个间隔图案。 在形成间隔物图案之后，在牺牲层中形成多个第一阻挡层。 在形成第一阻挡层之后，在衬底上形成多个第二阻挡层，暴露至少一部分牺牲层和至少一部分第一阻挡层。 接下来，用间隔物图案蚀刻牺牲层和硬掩模层，将第一阻挡层和第二阻挡层用作蚀刻掩模，以在基板上形成图案化的硬掩模层。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。