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    Semiconductor structure having a strained region and a method of fabricating same
    11.
    发明授权
    Semiconductor structure having a strained region and a method of fabricating same 有权
    具有应变区域的半导体结构及其制造方法

    公开(公告)号：US07495267B2

    公开(公告)日：2009-02-24

    申请号：US11409405

    申请日：2006-04-21

    申请人： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

    发明人： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

    IPC分类号： H01L31/0368

    CPC分类号： H01L29/78 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L29/7846

    摘要： A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

    摘要翻译： 包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。 顶层沉积在一系列一个或多个下层的最上面。 每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。 沟槽形成在最上层的层中。 沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。 通过在沟槽形成之后加热最上面的串联层来产生圆角。

    Strained silicon structure
    12.
    发明授权
    Strained silicon structure 有权
    应变硅结构

    公开(公告)号：US07208754B2

    公开(公告)日：2007-04-24

    申请号：US11114981

    申请日：2005-04-26

    申请人： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

    发明人： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

    摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.

    摘要翻译： 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于衬底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

    Strained silicon MOS devices
    13.
    发明申请
    Strained silicon MOS devices 有权
    应变硅MOS器件

    公开(公告)号：US20050032321A1

    公开(公告)日：2005-02-10

    申请号：US10637351

    申请日：2003-08-08

    申请人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

    发明人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

    摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

    摘要翻译： 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

    Novel CMOS device
    16.
    发明申请
    Novel CMOS device 审中-公开
    新型CMOS器件

    公开(公告)号：US20060138557A1

    公开(公告)日：2006-06-29

    申请号：US11356865

    申请日：2006-02-17

    申请人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    发明人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

    摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

    摘要翻译： 一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。 在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。 第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸 在NMOS器件上的应力层。

    CMOS device
    17.
    发明授权
    CMOS device 有权
    CMOS器件

    公开(公告)号：US07022561B2

    公开(公告)日：2006-04-04

    申请号：US10307619

    申请日：2002-12-02

    申请人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    发明人： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

    摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

    摘要翻译： 一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。 在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。 第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸 在NMOS器件上的应力层。

    Offset spacer formation for strained channel CMOS transistor
    20.
    发明申请
    Offset spacer formation for strained channel CMOS transistor 有权
    用于应变通道CMOS晶体管的偏移间隔物形成

    公开(公告)号：US20050247986A1

    公开(公告)日：2005-11-10

    申请号：US10840911

    申请日：2004-05-06

    申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

    发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

    摘要： A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.

    摘要翻译： 一种应变通道晶体管和用于形成包括半导体速率的应变通道晶体管的方法; 覆盖沟道区的栅极电介质; 栅极覆盖栅极电介质; 源极漏极延伸区域和源极和漏极（S / D）区域; 其中设置选自由围绕所述栅极环配置的应力偏移间隔的r和设置在包括所述S / D区的所述栅极周围的应力介电层的施放电介质部分以施加应变通道区域。