公开(公告)号：US08563989B2

公开(公告)日：2013-10-22

申请号：US13402882

申请日：2012-02-23

申请人： Chao-Shun Yang ,  Chen-Ming Hu

发明人： Chao-Shun Yang ,  Chen-Ming Hu

IPC分类号： H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L33/62 ,  H01L33/36 ,  H01L51/0021 ,  H01L51/5218 ,  H01L2251/5315 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer.

摘要翻译： 提供了一种发光器件的制造方法。 在基板上形成第一电极。 第一电极包括图案化的导电层，并且图案化的导电层包括含有第一金属和第二金属的合金。 在第一电极上执行退火处理，以至少在第一电极的侧表面上形成钝化层。 钝化层包括第二金属的化合物。 在第一电极上形成发光层。 在发光层上形成第二电极。

公开(公告)号：US06855994B1

公开(公告)日：2005-02-15

申请号：US09857453

申请日：1999-11-29

申请人： Ya-Chin King ,  Tsu-Jae King ,  Chen Ming Hu

发明人： Ya-Chin King ,  Tsu-Jae King ,  Chen Ming Hu

IPC分类号： H01L29/78 ,  C23C14/48 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L21/31 ,  H01L21/469 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： C23C14/48 ,  H01L21/823462 ,  Y10S438/92 ,  Y10S438/966 ,  Y10S438/974

摘要： A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.

摘要翻译： 一种半导体器件，包括多个晶体管的多个厚度的栅极氧化物，其中栅极氧化物厚度通过将氧离子注入到衬底的选定区域的生长过程而改变。 植入的氧离子加速了氧化物的生长，这也使得与金属间介电层相比，质量特别重要的氧化物层的质量和可靠性也是优异的。 已经使用了一种技术来改变在氧化生长过程中在硅晶片上生长的氧化物层的厚度，这是通过将氮气注入衬底的选定区域来实现的，氮离子阻碍氧化硅的生长，导致氧化物质量降低。 因此，期望通过注入的氧离子技术制造具有多个栅极氧化物厚度的半导体器件。

公开(公告)号：US20070205468A1

公开(公告)日：2007-09-06

申请号：US11746141

申请日：2007-05-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L27/092

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US07202139B2

公开(公告)日：2007-04-10

申请号：US10068928

申请日：2002-02-07

申请人： Yee-Chia Yeo ,  Fu Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Fu Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/78696 ,  H01L21/76251 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78603

摘要： An ultra thin MOSFET device structure located on an insulator layer, and a method of forming the ultra thin MOSFET device structure featuring a strained silicon channel located on the underlying insulator layer, has been developed. After epitaxial growth of a semiconductor alloy layer such as silicon-germanium (SiGe), on a first semiconductor substrate, a strained silicon channel layer, under biaxial tensile strain, is epitaxially grown on the underlying semiconductor alloy layer. Bonding of the strained silicon channel layer of the first semiconductor substrate, to a silicon oxide layer located on the surface of a second semiconductor substrate, is followed by a cleaving procedure performed at the interface of the strained silicon channel layer and the underlying semiconductor alloy layer, resulting in the desired configuration comprised of strained silicon channel layer-underlying insulator layer-second semiconductor substrate. The MOSFET device is then formed featuring the strained silicon channel layer, on the underlying silicon oxide layer, with enhanced carrier mobility realized as a result of the biaxial tensile strain of the silicon channel layer.

摘要翻译： 已经开发了位于绝缘体层上的超薄MOSFET器件结构，以及形成具有位于下面的绝缘体层上的应变硅沟道的超薄MOSFET器件结构的方法。 在第一半导体衬底上的半导体合金层（SiGe）外延生长之后，在双轴拉伸应变下的应变硅沟道层在下面的半导体合金层上外延生长。 第一半导体衬底的应变硅沟道层与位于第二半导体衬底的表面上的氧化硅层的接合之后，在应变硅沟道层和下面的半导体合金层的界面处进行切割程序 导致由应变硅沟道层下面的绝缘体层 - 第二半导体衬底构成的期望的构造。 然后，MOSFET器件的特征在于下层氧化硅层上的应变硅沟道层，由于硅沟道层的双轴拉伸应变而实现增强的载流子迁移率。

公开(公告)号：US06924181B2

公开(公告)日：2005-08-02

申请号：US10366220

申请日：2003-02-13

申请人： Chien-Chao Huang ,  Chao-Hsiung Wang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chen Ming Hu

发明人： Chien-Chao Huang ,  Chao-Hsiung Wang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chen Ming Hu

IPC分类号： H01L21/28 ,  H01L29/778 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/2807 ,  H01L29/7782 ,  Y10S438/933

摘要： A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.

摘要翻译： 应变硅层制造及其制造方法采用在应变硅层上形成的应变绝缘体材料层，其又形成在形成于松弛材料基板上的应变硅 - 锗合金材料层上。 应变绝缘体材料层提供增加的制造选择，其在制造应变硅层制造时提供增强的制造效率。

公开(公告)号：US06703271B2

公开(公告)日：2004-03-09

申请号：US10002031

申请日：2001-11-30

申请人： Yee-Chia Yeo ,  Chun Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L218238

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

摘要翻译： 已经开发了用于制造具有包含应变SiGe层的沟道区的CMOS器件的工艺。 该工艺的特点是在N阱和P阱区的顶表面上复合硅层的选择性生长。 复合硅层由夹在选择性生长的未掺杂硅层之间的薄的应变SiGe层组成。 SiGe层中Ge的含量在约20至40重量％之间，允许存在增加的载流子迁移率而不产生硅缺陷。 薄的二氧化硅栅极绝缘体从选择性地生长的硅层的顶部热生长，位于覆盖选择性生长的SiGe层上。

公开(公告)号：US20130153949A1

公开(公告)日：2013-06-20

申请号：US13402882

申请日：2012-02-23

申请人： Chao-Shun Yang ,  Chen-Ming Hu

发明人： Chao-Shun Yang ,  Chen-Ming Hu

IPC分类号： H01L33/62

CPC分类号： H01L33/62 ,  H01L33/36 ,  H01L51/0021 ,  H01L51/5218 ,  H01L2251/5315 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer.

摘要翻译： 提供了一种发光器件的制造方法。 在基板上形成第一电极。 第一电极包括图案化的导电层，并且图案化的导电层包括含有第一金属和第二金属的合金。 在第一电极上执行退火处理，以至少在第一电极的侧表面上形成钝化层。 钝化层包括第二金属的化合物。 在第一电极上形成发光层。 在发光层上形成第二电极。

公开(公告)号：US07659587B2

公开(公告)日：2010-02-09

申请号：US11746141

申请日：2007-05-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/00

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US07226832B2

公开(公告)日：2007-06-05

申请号：US11227264

申请日：2005-09-15

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/8238

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US06753229B1

公开(公告)日：2004-06-22

申请号：US09449063

申请日：1999-11-24

申请人： Ya-Chin King ,  Tsu-Jae King ,  Chen Ming Hu

发明人： Ya-Chin King ,  Tsu-Jae King ,  Chen Ming Hu

IPC分类号： H01L2100

CPC分类号： C23C14/48 ,  H01L21/823462 ,  Y10S438/92 ,  Y10S438/966 ,  Y10S438/974

摘要： A process for forming gate oxides of multiple thicknesses. Oxygen is implanted through a sacrificial oxide into selected regions of a silicon substrate according to a patterned photoresist mask. After stripping the sacrificial oxide, a thermal growth process produces a thicker oxide in the implanted regions than in the non-implanted regions. The oxygen-implanted oxide has excellent quality and thickness differentials of up to 20 Å may be obtained with relatively low oxygen implant doses. In an alternative process, a thin gate oxide may be grown prior to a polysilicon layer deposition, and oxygen is then implanted through the polysilicon according to a patterned photoresist mask. After stripping the photoresist, an anneal increases the thickness of the gate oxide in the implanted regions. In another embodiment, a high dielectric constant dielectric layer is deposited on the substrate prior to polysilicon deposition to limit subsequent silicon oxide growth.

摘要翻译： 一种形成多个厚度的栅氧化物的方法。 根据图案化的光致抗蚀剂掩模，将氧通过牺牲氧化物注入到硅衬底的选定区域中。 在剥离牺牲氧化物之后，热生长过程在注入区域中产生比在非注入区域中更厚的氧化物。 氧注入的氧化物具有优异的质量，并且可以用较低的氧注入剂量获得高达20埃的厚度差异。 在替代方法中，可以在多晶硅层沉积之前生长薄栅氧化物，然后根据图案化的光致抗蚀剂掩模将氧注入多晶硅。 在剥离光致抗蚀剂之后，退火会增加注入区域中的栅极氧化物的厚度。 在另一个实施例中，在多晶硅沉积之前在衬底上沉积高介电常数电介质层以限制随后的氧化硅生长。