利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

129 条记录 (耗时 0.038 秒)

    Digital transmitter
    11.
    发明授权
    Digital transmitter 有权
    数字发射机

    公开(公告)号：US07715494B2

    公开(公告)日：2010-05-11

    申请号：US11514637

    申请日：2006-08-31

    申请人： William J. Dally

    发明人： William J. Dally

    IPC分类号： H04L25/03

    CPC分类号： H04L25/03019 ,  H04B1/0483 ,  H04B1/1081 ,  H04B1/16 ,  H04B3/04 ,  H04L1/0042 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/03025 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01

    摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

    摘要翻译： 提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。 均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。 优选的均衡器包括使用查找表的FIR转换滤波器。 包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。 均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

    HIGH-RADIX INTERPROCESSOR COMMUNICATIONS SYSTEM AND METHOD
    12.
    发明申请
    HIGH-RADIX INTERPROCESSOR COMMUNICATIONS SYSTEM AND METHOD 有权
    高分辨率接口通信系统与方法

    公开(公告)号：US20090292855A1

    公开(公告)日：2009-11-26

    申请号：US12352443

    申请日：2009-01-12

    申请人： Steven L. Scott ,  Dennis C. Abts ,  William J. Dally

    发明人： Steven L. Scott ,  Dennis C. Abts ,  William J. Dally

    IPC分类号： G06F13/20

    CPC分类号： H04L45/7453 ,  G06F15/17362 ,  H04L45/00 ,  H04L45/28 ,  H04L45/566 ,  H04L45/745 ,  H04L49/15

    摘要： A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n×p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.

    摘要翻译： 具有多个处理器节点，多个第一路由器和多个第二路由器的高基数处理器通信系统和方法。 每个第一路由器连接到处理器节点和两个或更多个第二路由器。 每个第一路由器包括输入端口，输出端口，行总线，列通道和以n×p矩阵排列的多个子开关。 每行总线从多个输入端口之一接收数据，并将数据分配给多个子开关中的两个或多个。 每列将数据从一个或多个子交换分配到一个或多个输出端口。 每行行总线包括路由选择器，其中路由选择器包括路由选择表，该路由表选择每个分组的输出端口，并且通过一条行总线将分组路由到所选输出端口。

    SIGNALING SYSTEM WITH LOW-POWER AUT0MATIC GAIN CONTROL
    13.
    发明申请
    SIGNALING SYSTEM WITH LOW-POWER AUT0MATIC GAIN CONTROL 有权
    具有低功率自动增益控制的信号系统

    公开(公告)号：US20090201090A1

    公开(公告)日：2009-08-13

    申请号：US12366612

    申请日：2009-02-05

    申请人： William J. Dally ,  John W. Poulton

    发明人： William J. Dally ,  John W. Poulton

    IPC分类号： H03G3/10

    CPC分类号： H03G3/3036 ,  H03G3/3052 ,  H03K2005/00039

    摘要： An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.

    摘要翻译： 集成电路装置包括可变增益放大器，存储电路和增益控制更新电路。 可变增益放大器至少在第一间隔期间内在存储器电路内产生具有根据增益控制值的幅度的放大信号。 更新电路基于第一间隔期间的放大信号产生更新的增益控制值，并且在第一间隔的结论处将更新的增益控制值输出到要存储在其中的存储器电路。

    Digital clock recovery circuit
    15.
    发明授权
    Digital clock recovery circuit 有权
    数字时钟恢复电路

    公开(公告)号：US07257183B2

    公开(公告)日：2007-08-14

    申请号：US10178902

    申请日：2002-06-21

    申请人： William J. Dally ,  John H. Edmondson ,  Ramin Farjad-Rad

    发明人： William J. Dally ,  John H. Edmondson ,  Ramin Farjad-Rad

    IPC分类号： H03D3/24 ,  H03D3/18

    CPC分类号： H04L7/0331 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/0337 ,  Y10S331/02

    摘要： A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

    摘要翻译： 时钟恢复电路包括用于采样数据信号的采样器。 逻辑确定数据边缘是否落在驱动采样器的时钟边缘之前，并提供早期和晚期指示。 滤波器过滤早期和晚期指示，相位控制器根据滤波指示调整时钟的相位。 基于经滤波的指示，频率估计器估计数据和时钟之间的频率差，向相位控制器提供输入以进一步调整相位，以便连续校正频率差。

    Architectures for a single-stage grooming switch
    18.
    发明授权
    Architectures for a single-stage grooming switch 有权
    单阶段美容开关架构

    公开(公告)号：US06807186B2

    公开(公告)日：2004-10-19

    申请号：US10052233

    申请日：2002-01-17

    申请人： William J. Dally ,  John Edmondson ,  Donald A. Priore ,  Ephrem Wu ,  John W. Poulton

    发明人： William J. Dally ,  John Edmondson ,  Donald A. Priore ,  Ephrem Wu ,  John W. Poulton

    IPC分类号： H04L1228

    CPC分类号： H04L49/405 ,  H04Q3/521

    摘要： A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.

    摘要翻译： 提供单级梳理开关，用于在时域和空间域中切换多路复用业务流，如SONET STS-48。 特别地，交换机实现分布式解复用架构，用于在减少的布局大小的任何输入时隙之间切换到任何输出时隙。 此外，分布式解复用架构导致低延迟与纳秒级的输出排列的重新配置相关联。

    Serial-link circuit including capacitive offset adjustment of a high-speed receiver
    19.
    发明授权
    Serial-link circuit including capacitive offset adjustment of a high-speed receiver 失效
    串行链路电路包括高速接收机的电容偏移调整

    公开(公告)号：US06728240B1

    公开(公告)日：2004-04-27

    申请号：US09498413

    申请日：2000-02-04

    申请人： William J. Dally ,  Ming-Ju Lee

    发明人： William J. Dally ,  Ming-Ju Lee

    IPC分类号： H04L1250

    CPC分类号： H04L25/0292 ,  H03K5/133 ,  H03K5/2481 ,  H03K5/249 ,  H03K2005/00234 ,  H03L7/0812 ,  H04J3/04 ,  H04J3/0685 ,  H04L25/0274 ,  H04L25/0278 ,  H04L25/0286

    摘要： A serial link circuit includes a transmitter which multiplexes the circuit's input signals together and uses a single processing circuit to generate a multiplexed output to be transmitted. The multiplexing is done with a limited voltage swing prior to preamplification. In this way, clock loading (and hence clock buffer area), power and jitter are significantly reduced. The complementary link receiver includes a demultiplexer implemented with sense amplifiers that are digitally unbalanced using trimmer capacitors to cancel the receiver's offset voltage. This allows the receiver to be implemented using very small elements to save power, and enables the link to operate reliably with a very low signal swing.

    摘要翻译： 串行链路电路包括将电路的输入信号复用在一起的发送器，并且使用单个处理电路来生成要发送的多路复用输出。 在预放大之前，在有限的电压摆幅下进行复用。 以这种方式，时钟负载（因此时钟缓冲区），功率和抖动显着降低。 互补链路接收机包括用读出放大器实现的解复用器，其使用微调电容器进行数字不平衡，以消除接收机的偏移电压。 这允许使用非常小的元件实现接收器以节省功率，并且使链路能够以非常低的信号摆幅可靠地操作。