公开(公告)号：US20240274162A1

公开(公告)日：2024-08-15

申请号：US18109229

申请日：2023-02-13

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  David James RIDDOCH ,  Steven Leslie POPE

IPC: G11C7/10 ,  G11C7/24

CPC classification number: G11C7/1039 ,  G11C7/24

Abstract: An integrated circuit (IC) device includes functional circuits and multiple communication paths, which may include a first communication path through the functional circuits and a second communication path to permit the functional circuits to share information through a buffer and/or to bypass a subset of the functional circuits and a corresponding portion of the first communication path. The IC device may include a variety of protocol-specific interface circuits (ASIC and/or configurable circuitry) for respective IP blocks, and a controller that selectively directs traffic through the various communication paths. The controller may include a set of domain-specific OpCodes that link various subsets/combinations of the protocol-specific interface circuits as respective communication paths. The IC device may include multiple blocks of circuitry, each including a respective set of domain-specific circuitry (e.g., host-domain, network domain, RF domain, and/or data processing domain), and respective sets of OpCodes.

公开(公告)号：US20230325333A1

公开(公告)日：2023-10-12

申请号：US18206045

申请日：2023-06-05

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Millind MITTAL

IPC: G06F13/40 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F9/30043 ,  G06F13/1663 ,  G06F13/1668 ,  G06F2209/5011 ,  G06F2213/0038

Abstract: An integrated circuit (IC) for adaptive memory expansion scheme is proposed, which comprises: a home agent comprising a first memory expansion pool and a second memory expansion pool; a first port connecting the home agent to a first memory expansion device, where the first memory expansion device comprises a first memory pool; a second port connecting the home agent to a second memory expansion device, where the second memory expansion device comprises a second memory pool; a first address table mapping the first memory expansion pool to the first memory pool based on a size of the first memory expansion pool or a size of the first memory pool; and a second address table mapping the second memory expansion pool to the second memory pool based on a size of the second memory expansion pool or a size of the second memory pool.

公开(公告)号：US20230308384A1

公开(公告)日：2023-09-28

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Jaideep DASTIDAR ,  Jeffrey CUPPETT ,  Sagheer AHMAD

IPC: H04L49/109 ,  H04L45/24 ,  H04L45/74

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US20230195684A1

公开(公告)日：2023-06-22

申请号：US18112362

申请日：2023-02-21

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Millind MITTAL

IPC: G06F15/78 ,  G06N20/00 ,  G06F9/54 ,  G06F13/42 ,  H04L12/66 ,  G06F3/06

CPC classification number: G06F15/7825 ,  G06N20/00 ,  G06F9/544 ,  G06F9/546 ,  G06F13/4282 ,  H04L12/66 ,  G06F3/067 ,  G06F2213/0026

Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators previously only used an I/O domain. In the embodiments herein, compute resources can be split between the I/O domain and the coherent domain where a ML engine is in the I/O domain and a ML model is in the coherent domain. An advantage of doing so is that the ML model can be coherently updated using a reference ML model stored in the host.

公开(公告)号：US20230094621A1

公开(公告)日：2023-03-30

申请号：US17449561

申请日：2021-09-30

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  James MURRAY

IPC: G06F12/0817

Abstract: Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.

公开(公告)号：US20230328045A1

公开(公告)日：2023-10-12

申请号：US17716881

申请日：2022-04-08

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Jason MOORE ,  Brian S. MARTIN

IPC: H04L9/40 ,  H04L45/02

CPC classification number: H04L63/0435 ,  H04L63/0407 ,  H04L63/20 ,  H04L63/145 ,  H04L45/02

Abstract: Embodiments herein describe a SoC with one or more untrusted islands that can host one or more roles or tenants in a data center environment (e.g., a cloud computing environment). In one embodiment, a secure shell encapsulates the untrusted islands with a secure application programming interface (API) to access other hardware resources in the SoC. Hardware resources in the SoC (e.g., HardIP, SoftIP, or both), can either be secure/trusted, or rely on the secure shell to ensure confidentiality.

公开(公告)号：US20230229757A1

公开(公告)日：2023-07-20

申请号：US17578292

申请日：2022-01-18

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  James MURRAY ,  Stefano STABELLINI

IPC: G06F21/53 ,  G06F9/455

CPC classification number: G06F21/53 ,  G06F9/45558 ,  G06F2009/45587 ,  G06F2009/45579

Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.

公开(公告)号：US20230177146A1

公开(公告)日：2023-06-08

申请号：US17457839

申请日：2021-12-06

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Aman GUPTA ,  Krishnan SRINIVASAN ,  Sagheer AHMAD

IPC: G06F21/54 ,  G06F21/85 ,  G06F21/62

CPC classification number: G06F21/54 ,  G06F21/85 ,  G06F21/6209

Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.

公开(公告)号：US20220269638A1

公开(公告)日：2022-08-25

申请号：US17184456

申请日：2021-02-24

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR

IPC: G06F13/42 ,  G06F21/60

Abstract: The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.

公开(公告)号：US20210064529A1

公开(公告)日：2021-03-04

申请号：US16560217

申请日：2019-09-04

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Millind MITTAL

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/121

Abstract: The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.