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    Core for a data processing engine in an integrated circuit
    12.
    发明授权
    Core for a data processing engine in an integrated circuit 有权

    公开(公告)号：US10747531B1

    公开(公告)日：2020-08-18

    申请号：US15944315

    申请日：2018-04-03

    Applicant: Xilinx, Inc.

    Inventor： Jan Langer ,  Baris Ozgul ,  Juan J. Noguera Serra ,  Goran HK Bilski ,  Tim Tuan

    IPC: G06F9/302 ,  G06F7/57 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F7/499 ,  G06F15/80

    Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.

    MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
    14.
    发明公开
    MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY 审中-公开

    公开(公告)号：US20230289311A1

    公开(公告)日：2023-09-14

    申请号：US18320147

    申请日：2023-05-18

    Applicant: Xilinx, Inc.

    Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

    IPC: G06F13/40 ,  G06F13/16

    CPC classification number: G06F13/4027 ,  G06F13/1668

    Abstract: An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

    Multi-die integrated circuit with data processing engine array
    15.
    发明授权
    Multi-die integrated circuit with data processing engine array 有权

    公开(公告)号：US11693808B2

    公开(公告)日：2023-07-04

    申请号：US17654543

    申请日：2022-03-11

    Applicant: Xilinx, Inc.

    Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

    IPC: G06F13/40 ,  G06F13/16

    CPC classification number: G06F13/4027 ,  G06F13/1668

    Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.

    MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
    17.
    发明申请
    MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY 有权

    公开(公告)号：US20220197846A1

    公开(公告)日：2022-06-23

    申请号：US17654543

    申请日：2022-03-11

    Applicant: Xilinx, Inc.

    Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

    IPC: G06F13/40 ,  G06F13/16

    Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.

    Activity-aware clock gating for switches
    18.
    发明授权
    Activity-aware clock gating for switches 有权

    公开(公告)号：US11223351B1

    公开(公告)日：2022-01-11

    申请号：US17163189

    申请日：2021-01-29

    Applicant: XILINX, INC.

    Inventor： Amarnath Kasibhatla ,  Saurabh Mathur ,  Mansi Shrikant Patwardhan ,  Tim Tuan

    IPC: H03K17/28 ,  G06F1/04 ,  H03K17/00

    Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

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