公开(公告)号：US20210303509A1

公开(公告)日：2021-09-30

申请号：US17099587

申请日：2020-11-16

Applicant: XILINX, INC.

Inventor： Ian Andrew SWARBRICK ,  Sagheer AHMAD ,  Ygal ARBEL ,  Dinesh GAITONDE

IPC: G06F15/78 ,  G06F13/42 ,  H04L12/40 ,  H04L12/717 ,  H04L12/773

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

公开(公告)号：US20250167152A1

公开(公告)日：2025-05-22

申请号：US19032979

申请日：2025-01-21

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Kenneth MA ,  Balakrishna JAYADEV ,  Sagheer AHMAD

IPC: H01L23/00 ,  G11C5/06 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US20250068583A1

公开(公告)日：2025-02-27

申请号：US18238369

申请日：2023-08-25

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL

IPC: G06F15/78

Abstract: Embodiments herein describe using virtual destinations to route packets through a NoC. In one embodiment, instead of decoding an address into a target destination ID of the NoC, an ingress logic block assigns packets for multiple different targets the same virtual destination ID. For example, these targets may be in the same segment or location of the NoC. Thus, instead of the ingress logic block having to store entries in a lookup-table for each target, it can have a single entry for the virtual destination ID. The packets for the targets are then routed using the virtual destination ID to a decoder switch in the NoC. This decoder switch can then use the address in the packet (which is different than the destination ID) to select the appropriate target destination ID.

公开(公告)号：US20240411715A1

公开(公告)日：2024-12-12

申请号：US18807703

申请日：2024-08-16

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL ,  Millind MITTAL

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

公开(公告)号：US20240333473A1

公开(公告)日：2024-10-03

申请号：US18126877

申请日：2023-03-27

Applicant: XILINX, INC.

Inventor： Abbas MORSHED ,  Ygal ARBEL

IPC: H04L9/06 ,  G06F12/1009 ,  G06F12/12

CPC classification number: H04L9/0637 ,  G06F12/1009 ,  G06F12/12 ,  H04L9/0631

Abstract: Some examples described herein provide for an encrypted data quantization apparatus and method, for example a memory controller to quantize encrypted data using a cache. One or more embodiments includes obtaining a first set of plaintext data bits to be stored in a memory device using an encryption scheme. A memory address for encrypted data bits to be stored in the memory device is identified for a first subset of plaintext data bits. A second set of plaintext data bits associated with the memory address is obtained from a cache, if present. The second set of plaintext data bits are modified according to the first set of plaintext data bits to be stored in the memory device to generate a third set of plaintext data bits that are then encoded according to the encryption scheme for storage in the memory device.

公开(公告)号：US20240045822A1

公开(公告)日：2024-02-08

申请号：US17879675

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Abbas MORSHED

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

公开(公告)号：US20240014161A1

公开(公告)日：2024-01-11

申请号：US18369115

申请日：2023-09-15

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Kenneth MA ,  Balakrishna JAYADEV ,  Sagheer AHMAD

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L25/0657 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2924/1434 ,  H01L2225/0651

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US20230376248A1

公开(公告)日：2023-11-23

申请号：US18226193

申请日：2023-07-25

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Ian A. SWARBRICK ,  Sagheer AHMAD

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28 ,  G06F1/3287

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F13/4022 ,  G06F1/28 ,  G06F3/0679 ,  G06F1/3287 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US20230066736A1

公开(公告)日：2023-03-02

申请号：US17464642

申请日：2021-09-01

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Sagheer AHMAD ,  Ygal ARBEL

IPC: G06F13/42 ,  G06F13/40

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

公开(公告)号：US20210303508A1

公开(公告)日：2021-09-30

申请号：US16830142

申请日：2020-03-25

Applicant: XILINX, INC.

Inventor： Abbas MORSHED ,  Ygal ARBEL ,  Eun Mi KIM

IPC: G06F15/78 ,  G06F5/10 ,  G06F9/38 ,  G06F13/40

Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.