公开(公告)号：US08692322B2

公开(公告)日：2014-04-08

申请号：US13539330

申请日：2012-08-26

申请人： Ji Pan ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

发明人： Ji Pan ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

摘要翻译： 半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘 栅极沟槽的部分通过电极间绝缘层。 晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元， 连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

公开(公告)号：US08637368B2

公开(公告)日：2014-01-28

申请号：US13559975

申请日：2012-07-27

申请人： Anup Bhalla ,  Xiaobin Wang

发明人： Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.

摘要翻译： 制造半导体器件包括：在覆盖半导体衬底的外延层中形成栅极沟槽; 在门沟中设置栅极材料; 在外延层中形成主体; 在身体中形成一个来源; 形成具有变化的沟槽深度的有源区接触沟槽; 以及将接触电极设置在有源区接触沟槽内。 形成有源区接触沟槽包括执行第一蚀刻以形成与第一区域相关联的第一接触沟槽深度，以及执行第二蚀刻以形成与第二区域相关联的第二接触沟槽深度。 第一接触沟槽深度与第二接触沟槽深度基本不同。

公开(公告)号：US08519495B2

公开(公告)日：2013-08-27

申请号：US12372025

申请日：2009-02-17

申请人： Insik Jin ,  Hongyue Liu ,  Yong Lu ,  Xiaobin Wang

发明人： Insik Jin ,  Hongyue Liu ,  Yong Lu ,  Xiaobin Wang

IPC分类号： H01L29/82

CPC分类号： H01L43/08 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228

摘要： A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.

摘要翻译： 磁存储器件包括通过磁性隧道结从第二电极分离的第一电极。 第一电极沿着第一电极的长度提供写入电流路径。 磁性隧道结包括具有可在高电阻状态磁化取向和低电阻状态磁化取向之间切换的磁化取向的自由磁性层。 自由磁性层与第一电极间隔小于10纳米的距离。 沿着写入电流路径的电流产生磁场。 磁场在高电阻状态磁化取向和低电阻状态磁化取向之间切换自由磁层磁化取向。

公开(公告)号：US08482971B2

公开(公告)日：2013-07-09

申请号：US13472867

申请日：2012-05-16

申请人： Xuguang Wang ,  Yiran Chen ,  Dimitar V. Dimitrov ,  Hongyue Liu ,  Xiaobin Wang

发明人： Xuguang Wang ,  Yiran Chen ,  Dimitar V. Dimitrov ,  Hongyue Liu ,  Xiaobin Wang

IPC分类号： G11C11/14

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659

摘要： A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

摘要翻译： 存储器阵列包括位线和源极线的交叉点阵列。 存储器设置在交叉点阵列的交叉点处。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 晶体管电连接在磁性隧道结数据单元与位线或源极线之间，二极管与磁性隧道结数据单元处于热或电接触以辅助电阻状态切换。

公开(公告)号：US08481181B2

公开(公告)日：2013-07-09

申请号：US13077946

申请日：2011-03-31

申请人： Xiaobin Wang ,  Kaizhong Gao

发明人： Xiaobin Wang ,  Kaizhong Gao

IPC分类号： G11B5/65

CPC分类号： G11B5/66 ,  Y10T428/115

摘要： Approaches to reduce switching field distribution in energy assisted magnetic storage devices involve first and second exchange coupled magnetic elements. The first magnetic elements have anisotropy, Hk1, volume, V1 and the second magnetic elements are magnetically exchange coupled to the first magnetic elements and have anisotropy Hk2, and volume V2. The thermal stability of the exchange coupled magnetic elements is greater than about 60 kBT at a storage temperature of about 300 K. The magnetic switching field distribution, SFD, of the exchange coupled magnetic elements is less than about 200% at a predetermined magnetic switching field and a predetermined assisting switching energy.

摘要翻译： 降低能量辅助磁存储装置中的开关场分布的方法包括第一和第二交换耦合磁性元件。 第一磁性元件具有各向异性Hk1，体积V1，第二磁性元件磁耦合到第一磁性元件并具有各向异性Hk2和体积V2。 在约300K的存储温度下，交换耦合磁性元件的热稳定性大于约60kBT。交换耦合磁性元件的磁开关场分布SFD在预定的磁切换场下小于约200％ 和预定的辅助切换能量。

公开(公告)号：US08354316B2

公开(公告)日：2013-01-15

申请号：US12925820

申请日：2010-10-29

申请人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

发明人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

IPC分类号： H01L21/8234

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

公开(公告)号：US08289758B2

公开(公告)日：2012-10-16

申请号：US12943979

申请日：2010-11-11

申请人： Yuankai Zheng ,  Dimitar V. Dimitrov ,  Wei Tian ,  Dexin Wang ,  Zheng Gao ,  Xiaobin Wang

发明人： Yuankai Zheng ,  Dimitar V. Dimitrov ,  Wei Tian ,  Dexin Wang ,  Zheng Gao ,  Xiaobin Wang

IPC分类号： G11C11/16

CPC分类号： G11C11/161

摘要： Magnetic tunnel junctions having a specular insulative spacer are disclosed. The magnetic tunnel junction includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, and an electrically insulating and electronically reflective layer positioned to reflect at least a portion of electrons back into the free magnetic layer.

摘要翻译： 公开了具有镜面绝缘间隔物的磁隧道结。 磁性隧道结包括自由磁性层，参考磁性层，将自由磁性层与参考磁性层分离的电绝缘和非磁性隧道势垒层，以及电绝缘和电子反射层，其被定位成反射至少一个 部分电子返回自由磁性层。

公开(公告)号：US08253192B2

公开(公告)日：2012-08-28

申请号：US13088275

申请日：2011-04-15

申请人： Anup Bhalla ,  Xiaobin Wang

发明人： Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width.

摘要翻译： 半导体器件包括：漏区，包括外延层，设置在外延层中的主体，嵌入在主体中的源极，延伸到外延层中的栅极沟槽，设置在栅极沟槽中的栅极，有源区域接触沟槽延伸 通过源极，以及设置在有源区接触沟槽内的有源区接触电极。 有源区接触沟槽具有与位于本体底部附近的第一区域相关联的第一宽度和与源极底部附近的第二区域相关联的第二宽度。 第一宽度与第二宽度大致不同。

公开(公告)号：US08247329B2

公开(公告)日：2012-08-21

申请号：US13024256

申请日：2011-02-09

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L21/311

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构来形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

公开(公告)号：US08213215B2

公开(公告)日：2012-07-03

申请号：US13015085

申请日：2011-01-27

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/06

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C27/02 ,  G11C2013/0057 ,  G11C2207/2254

摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.

摘要翻译： 描述了自参考读取方法的电阻记忆校准。 读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。 电阻存储器单元形成存储器阵列。 通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻性存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态 每个电阻存储器单元。 然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同 作为第一电阻数据状态。