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    Nanotube semiconductor devices
    1.
    发明授权
    Nanotube semiconductor devices 有权
    纳米管半导体器件

    公开(公告)号：US08247329B2

    公开(公告)日：2012-08-21

    申请号：US13024256

    申请日：2011-02-09

    申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    IPC分类号： H01L21/311

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

    摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

    摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构来形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

    Method for forming nanotube semiconductor devices
    2.
    发明授权
    Method for forming nanotube semiconductor devices 有权
    形成纳米管半导体器件的方法

    公开(公告)号：US07910486B2

    公开(公告)日：2011-03-22

    申请号：US12484166

    申请日：2009-06-12

    申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    IPC分类号： H01L21/311

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

    摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

    摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

    Method for Forming Nanotube Semiconductor Devices
    4.
    发明申请
    Method for Forming Nanotube Semiconductor Devices 有权
    形成纳米管半导体器件的方法

    公开(公告)号：US20100317158A1

    公开(公告)日：2010-12-16

    申请号：US12484166

    申请日：2009-06-12

    申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/329

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

    摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

    摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

    Nanotube Semiconductor Devices
    6.
    发明申请
    Nanotube Semiconductor Devices 有权
    纳米管半导体器件

    公开(公告)号：US20110140167A1

    公开(公告)日：2011-06-16

    申请号：US13024256

    申请日：2011-02-09

    申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

    IPC分类号： H01L29/739 ,  H01L21/331

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

    摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

    摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions
    7.
    发明申请
    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
    用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法

    公开(公告)号：US20100314682A1

    公开(公告)日：2010-12-16

    申请号：US12661004

    申请日：2010-03-05

    申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

    摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

    摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions
    8.
    发明授权
    Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions 有权
    用于制造具有沟槽氧化物 - 纳米管超结的器件的配置和方法

    公开(公告)号：US08390058B2

    公开(公告)日：2013-03-05

    申请号：US12661004

    申请日：2010-03-05

    申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

    摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

    摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

    Shielded gate trench MOSFET device and fabrication
    9.
    发明申请
    Shielded gate trench MOSFET device and fabrication 有权
    屏蔽栅沟槽MOSFET器件和制造

    公开(公告)号：US20110037120A1

    公开(公告)日：2011-02-17

    申请号：US12583191

    申请日：2009-08-14

    申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

    发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

    摘要翻译： 半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。 非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。 另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。 源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。 另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。