公开(公告)号：US10243882B1

公开(公告)日：2019-03-26

申请号：US15486969

申请日：2017-04-13

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Sagheer Ahmad

IPC: H03K19/177 ,  H04L12/933 ,  H04L12/741

Abstract: A disclosed network on chip includes a semiconductor die and switches disposed on the semiconductor die. Each switch has ports configured to receive packets from and transmit packets to at least two other switches. Each switch includes first circuitry that specifies a first mapping of interface identifiers of interfaces on the semiconductor die to port identifiers, and second circuitry that specifies a second mapping of region identifiers of regions of the semiconductor die to port identifiers. Each switch further includes third circuitry coupled to the first and second circuitry. The third circuitry is configured to select, in response to an input packet that specifies a destination region and a destination interface, a port based on the specification of the destination region, specification of the destination interface, first mapping, and second mapping, and output the packet on the selected port.

公开(公告)号：US11709624B2

公开(公告)日：2023-07-25

申请号：US15898183

申请日：2018-02-15

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28 ,  G06F1/3287

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F1/3287 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/4022 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US11281810B1

公开(公告)日：2022-03-22

申请号：US16216986

申请日：2018-12-11

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick

IPC: G06F21/76 ,  G06F21/78 ,  H03K19/17768 ,  G06F12/14

Abstract: Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable logic region. The interconnect is communicatively coupled to the control logic. The interconnect is operable to communicate the memory transaction request therethrough. The memory controller is communicatively coupled to the interconnect. The memory controller is operable to receive the memory transaction request. The memory controller is configurable to determine whether the memory transaction request is permitted based on the one or more transaction attributes.

公开(公告)号：US20200327089A1

公开(公告)日：2020-10-15

申请号：US16380860

申请日：2019-04-10

Applicant: Xilinx, Inc.

Inventor： Jaideep Dastidar ,  Sagheer Ahmad ,  Ian A. Swarbrick

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/40

Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).

公开(公告)号：US20200092230A1

公开(公告)日：2020-03-19

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US20190250853A1

公开(公告)日：2019-08-15

申请号：US15898183

申请日：2018-02-15

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F1/3287 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/4022 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US20230291405A1

公开(公告)日：2023-09-14

申请号：US18320168

申请日：2023-05-18

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/17712

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

公开(公告)号：US10936486B1

公开(公告)日：2021-03-02

申请号：US16282081

申请日：2019-02-21

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick

IPC: G06F12/00 ,  G06F12/06

Abstract: Techniques for providing address interleave support in a programmable device are described. In an example, a programmable integrated circuit (IC) includes a processing system, programmable logic, a plurality of master circuits disposed in the processing system, the programmable logic, or both the processing system and the programmable logic, an address interleave and transaction chopping circuit, a memory having a plurality of channels, and a system interconnect configured to couple the address interleave and transaction chopping circuit to the memory. The address interleave and transaction chopping circuit is configured to interleave memory transactions from the plurality of master circuits across the plurality of channels of the memory at a selected boundary.

公开(公告)号：US10893005B2

公开(公告)日：2021-01-12

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933 ,  H04L12/761

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US10817455B1

公开(公告)日：2020-10-27

申请号：US16380860

申请日：2019-04-10

Applicant: Xilinx, Inc.

Inventor： Jaideep Dastidar ,  Sagheer Ahmad ,  Ian A. Swarbrick

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/28

Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).