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11.发明授权公开(公告)号：US11901313B2
公开(公告)日：2024-02-13
申请号：US17830250
申请日：2022-06-01
发明人： Kun Zhang , Linchun Wu , Zhong Zhang , Wenxi Zhou , Zongliang Huo
CPC分类号： H01L23/562 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B43/27 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.
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公开(公告)号：US20230225124A1
公开(公告)日：2023-07-13
申请号：US18081614
申请日：2022-12-14
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Shuangshuang Wu , Zhiliang Xia , Zongliang Huo
摘要： A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure, and a slit structure extending through the stack structure along the first direction. The slit structure includes a slit core, and a second dielectric layer surrounding the slit core. A first width of the second dielectric layer near the first semiconductor layer is larger than a second width of the second dielectric layer away from the first semiconductor layer.
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公开(公告)号：US20230189516A1
公开(公告)日：2023-06-15
申请号：US17648783
申请日：2022-01-24
发明人： Tao Yang , DongXue Zhao , Yuancheng Yang , Lei Liu , Kun Zhang , Di Wang , Wenxi Zhou , ZhiLiang Xia , ZongLiang Huo
IPC分类号： H01L27/11556 , G11C5/02 , H01L27/11582 , H01L23/532
CPC分类号： H01L27/11556 , G11C5/025 , H01L27/11582 , H01L23/53204
摘要： The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.
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公开(公告)号：US20230142290A1
公开(公告)日：2023-05-11
申请号：US17646549
申请日：2021-12-30
发明人： DongXue ZHAO , Tao Yang , Yuancheng Yang , Lei Liu , Di Wang , Kun Zhang , Wenxi Zhou , Zhiliang Xia , ZongLiang Huo
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/30
摘要： This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.
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公开(公告)号：US20230118742A1
公开(公告)日：2023-04-20
申请号：US18083339
申请日：2022-12-16
发明人： Linchun Wu , Kun Zhang , Zhong Zhang , Wenxi Zhou , Zhiliang Xia
摘要： A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.
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公开(公告)号：US11621275B2
公开(公告)日：2023-04-04
申请号：US17020457
申请日：2020-09-14
发明人： Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11521 , H01L27/11582 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11568
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.
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公开(公告)号：US20230056340A1
公开(公告)日：2023-02-23
申请号：US17570091
申请日：2022-01-06
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Wei Xie , Di Wang , Bingguo Wang , Zongliang Huo
IPC分类号： H01L27/11582 , H01L27/11556
摘要： A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.
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公开(公告)号：US20230005944A1
公开(公告)日：2023-01-05
申请号：US17747877
申请日：2022-05-18
发明人： Kun Zhang , Lei Liu , Tao Yang , Linchun Wu , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11526 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a stack structure includes interleaved dielectric layers and conductive layers, a channel structure extending in the stack structure, and a doped semiconductor layer arranged on the stack structure. The doped semiconductor layer covers an end of the channel structure and the stack structure, the channel structure includes a channel layer, and the channel layer includes a doped channel layer.
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公开(公告)号：US20230005875A1
公开(公告)日：2023-01-05
申请号：US17510779
申请日：2021-10-26
发明人： Yanwei Shi , Yanhong Wang , Cheng Gan , Liang Chen , Wei Liu , Zhiliang Xia , Wenxi Zhou , Kun Zhang , Yuancheng Yang
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00 , H01L27/11529 , H01L27/11573 , G11C16/04 , G11C16/24
摘要： In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.
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公开(公告)号：US20230005862A1
公开(公告)日：2023-01-05
申请号：US17481875
申请日：2021-09-22
发明人： Yanhong Wang , Wei Liu , Liang Chen , Zhiliang Xia , Wenxi Zhou , Kun Zhang , Yuancheng Yang
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.
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