公开(公告)号：US20090014724A1

公开(公告)日：2009-01-15

申请号：US12230954

申请日：2008-09-09

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnumo

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnumo

IPC分类号： H01L33/00

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

摘要翻译： 本发明提供一种具有高操作性能和高可靠性的半导体器件。 在形成驱动电路的n沟道TFT 802中配置与栅极配线重叠的LDD区域707，能够实现高耐热载流子注入的TFT结构。 不与栅极布线重叠的LDD区域717,718,719和720被布置在形成像素单元的n沟道TFT 804中。 结果，实现了具有小的截止电流值的TFT结构。 在这种情况下，属于周期表第15族的元素在LDD区707中比在LDD区717,718,719和720中的浓度更高。

公开(公告)号：US07411535B2

公开(公告)日：2008-08-12

申请号：US10900921

申请日：2004-07-28

申请人： Yukio Tanaka

发明人： Yukio Tanaka

IPC分类号： H03M1/66

CPC分类号： H03M1/66 ,  G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0289 ,  H03M1/662 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

摘要翻译： 根据本发明的具有开关swD的AD / A转换电路允许通过首先施加第一电压（电压近似）来以更高速度执行电压（真正灰度电压）的写入操作 到没有通过电阻器元件而提供的真实灰度电压）输出到输出线，然后将经由电阻器元件提供的第二电压（真实灰度电压）施加到输出线。 因此，本发明可以提供一种能够以更高的速度以更高的精度将显示数据写入液晶单元的D / A转换电路，以及利用这种D / A转换电路的半导体器件。

公开(公告)号：US07342565B2

公开(公告)日：2008-03-11

申请号：US10762082

申请日：2004-01-21

申请人： Yukio Tanaka

发明人： Yukio Tanaka

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3633 ,  G09G2310/027 ,  G09G2310/0283

摘要： To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inverter circuit and an inverter circuit connected in series. The plurality of digital data latch circuits has a first N-channel Tr and a second N-channel Tr of which the sources or the drains are connected in series, a P-channel Tr, and a data holding circuit. The clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock signal and a start pulse to thereby feed the timing signal to the register circuit neighboring a register circuit and to a gate electrode of the first N-channel Tr and the P-channel Tr feeds a first electric voltage to the data holding circuit in accordance with a Res signal inputted to the gate electrode. The second N-channel Tr then takes in digital data on the basis of the timing signal to thereby output the digital data to the source or the drain of the first N-channel Tr. The timing signal outputted from the register circuit neighboring a register circuit is fed to the gate electrode of the first N-channel Tr.

摘要翻译： 提供简单且具有小表面积的驱动电路。 驱动器电路包括移位寄存器电路和多个锁存电路。 移位寄存器电路由具有时钟反相器电路和串联连接的反相器电路的多个寄存器电路组成。 多个数字数据锁存电路具有其源极或漏极串联连接的第一N沟道Tr和第二N沟道Tr，P沟道Tr和数据保持电路。 时钟反相器电路和反相器电路基于时钟信号和起始脉冲产生定时信号，从而将定时信号馈送到与寄存器电路相邻的寄存器电路和第一N沟道Tr的栅电极， P沟道Tr根据输入到栅电极的Res信号向数据保持电路馈送第一电压。 第二N信道Tr然后基于定时信号接收数字数据，从而将数字数据输出到第一N信道Tr的源或漏极。 从与寄存器电路相邻的寄存器电路输出的定时信号被馈送到第一N沟道Tr的栅电极。

公开(公告)号：US20070200113A1

公开(公告)日：2007-08-30

申请号：US11730087

申请日：2007-03-29

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

IPC分类号： H01L29/04

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

摘要翻译： 本发明提供一种具有高操作性能和高可靠性的半导体器件。 在形成驱动电路的n沟道TFT 802中配置与栅极配线重叠的LDD区域707，能够实现高耐热载流子注入的TFT结构。 不与栅极布线重叠的LDD区域717,718,719和720被布置在形成像素单元的n沟道TFT 804中。 结果，实现了具有小的截止电流值的TFT结构。 在这种情况下，属于周期表第15族的元素在LDD区707中比在LDD区717,718,719和720中的浓度更高。

公开(公告)号：US07204558B2

公开(公告)日：2007-04-17

申请号：US11425002

申请日：2006-06-19

申请人： Yukio Tanaka

发明人： Yukio Tanaka

IPC分类号： B60R22/28

CPC分类号： B60N2/818 ,  B60N2/815

摘要： Provided is an automobile headrest which can be prevented from being drawn out inadvertently or on purpose, and can be drawn out through a special operation if necessary. The automobile headrest includes a falloff preventing mechanism that can be composed of the same components as those of a height adjusting mechanism to be used. In the automobile headrest, a headrest stay is inserted in a headrest bush provided with a height adjusting mechanism. The headrest stay is provided with a height adjusting notch and a falloff preventing notch. The height adjusting mechanism can also serve as one headrest falloff preventing mechanism, so the height adjusting mechanism can lock and unlock the headrest. Another headrest stay is provided with a falloff preventing notch. Another headrest bush in which the other headrest stay is inserted is provided with the headrest falloff preventing mechanism including a lock member. The lock member is provided to abut on the other headrest stay inserted in the other headrest bush due to a resilient force of a spring so as to be capable of reciprocating. The lock member engages with the falloff preventing notch of the other headrest stay to prevent the headrest from falling off, and disengages from the falloff preventing notch when the lock member is operated against the resilient force of the spring. The falloff preventing notches arranged in both headrest stays are provided at different height positions.

摘要翻译： 提供一种汽车头枕，其可以防止被意外地或者故意地抽出，并且如果需要可以通过特殊的操作被抽出。 汽车头枕包括防滑机构，其可以由与要使用的高度调节机构相同的部件组成。 在汽车头枕中，在设置有高度调节机构的头枕中插入头枕支架。 头枕支架设有高度调节槽和防跌落槽。 高度调节机构也可以作为一个头枕防滑机构，因此高度调节机构可以锁定和解锁头枕。 另一个头枕支架设有防滑凹槽。 设置有另一个头枕支架插入的另一个头枕衬套设置有包括锁定构件的头枕防倾倒机构。 锁定构件被设置成由于弹簧的弹力而抵接在另一个头枕中的另一个头枕支架上，以便能够往复运动。 锁定构件与另一个头枕支撑件的防滑凹口接合，以防止头枕脱落，并且当锁定构件克服弹簧的弹力而被操作时，防止凹部脱离。 设置在两个头枕支架中的防止凹口的防震设置在不同的高度位置。

公开(公告)号：US07154466B2

公开(公告)日：2006-12-26

申请号：US11052143

申请日：2005-02-07

申请人： Mitsuaki Osame ,  Yukio Tanaka

发明人： Mitsuaki Osame ,  Yukio Tanaka

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3655 ,  G09G2320/0214

摘要： In executing the opposing common inverse drive in an active matrix-type semiconductor display device, a gate bias is suppressed to be comparable with that of the conventional inverse drive to avoid a range in which the off current jumps up and, hence, to suppress the leakage of the stored electric charge, thereby to maintain an ON/OFF margin of the pixel TFTs. The gate bias applied to the pixel TFT is maintained to be near the customarily employed voltage to maintain a gate breakdown voltage, and the electric power is consumed in a decreased amount by the drive circuit as a whole, thereby to provide a novel drive circuit. In the semiconductor display device, a tristate buffer is used for a gate signal line drive circuit, and different buffer potentials are applied depending upon a frame in which the opposing common potential assumes a positive sign and a frame in which the opposing common potential assumes a negative sign, thereby to maintain an ON/OFF margin of the pixel TFTs. The voltage amplitude is decreased during the opposing common inverse drive.

摘要翻译： 在有源矩阵型半导体显示装置中执行相对的公共反向驱动时，抑制栅极偏压与传统的反向驱动相当，以避免关断电流跳跃的范围，从而抑制 存储电荷的泄漏，从而保持像素TFT的ON / OFF边缘。 施加到像素TFT的栅极偏置保持接近通常采用的电压以保持栅极击穿电压，并且通过驱动电路作为整体以降低的量消耗电力，从而提供新颖的驱动电路。 在半导体显示装置中，三态缓冲器用于栅极信号线驱动电路，并且根据相对的公共电位呈现正号的帧和相对的共同电位呈现为的帧，施加不同的缓冲电位 从而保持像素TFT的ON / OFF边缘。 在相反的公共反向驱动期间，电压幅度减小。

公开(公告)号：US07079121B2

公开(公告)日：2006-07-18

申请号：US09928988

申请日：2001-08-15

申请人： Jun Koyama ,  Yukio Tanaka ,  Yasushi Kubota ,  Tamotsu Sakai

发明人： Jun Koyama ,  Yukio Tanaka ,  Yasushi Kubota ,  Tamotsu Sakai

IPC分类号： G09G3/36

CPC分类号： H01L27/124 ,  G02F1/1362 ,  G02F2001/13629 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2320/0209 ,  G09G2320/0223

摘要： A driving circuit of a liquid crystal display device including a first insulating substrate on which a plurality of signal lines and a plurality of scan lines are disposed, and pixel transistors made of thin film transistors are disposed in matrix at intersection points of those lines; a second insulating substrate opposite to the first insulating substrate; and a liquid crystal held between the first and second insulating substrates, in which the driving circuit is disposed on the first insulating substrate; each of clock lines or base portions of the clock lines for supplying clock signals to the driving circuit is made of a two-layer structure of the same wiring material as a gate electrode of the thin film transistor and the same wiring material as a source electrode or drain electrode of the thin film transistor; and a wiring line crossing the clock lines or the base portions of the clock lines is made of a wiring line in the same layer as a black matrix covering the pixel transistors.

公开(公告)号：US07075510B2

公开(公告)日：2006-07-11

申请号：US10355404

申请日：2003-01-31

申请人： Yukio Tanaka ,  Keisuke Hayashi

发明人： Yukio Tanaka ,  Keisuke Hayashi

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0224 ,  G09G2310/027 ,  G09G2310/0281 ,  G11C19/28 ,  H01L27/12 ,  H01L27/1214

摘要： There is provided a driving circuit which is simple and has a small occupied area. A shift register circuit of the present invention includes a plurality of register circuits. Each of the register circuits includes a clocked inverter circuit and an inverter circuit. Both are connected in series with each other so that an output signal of the clocked inverter circuit becomes an input signal of the inverter circuit. Further, the register circuit includes a signal line by which an output signal of the inverter circuit is transmitted. Since a number of elements are connected to the signal line and parasitic capacitance is large, it has a high load. The shift register circuit of the present invention uses the fact that since the parasitic capacitance of the signal line is large, it has a high load.

公开(公告)号：US20060092111A1

公开(公告)日：2006-05-04

申请号：US11254683

申请日：2005-10-21

申请人： Kenji Nakao ,  Seiji Kawaguchi ,  Yukio Tanaka

发明人： Kenji Nakao ,  Seiji Kawaguchi ,  Yukio Tanaka

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3655 ,  G09G2300/0491 ,  G09G2320/0276

摘要： A liquid crystal display device comprises a display panel including a pair of electrode substrates and a liquid crystal layer that is held between the electrode substrates and contains a liquid crystal material whose molecules are transferred in advance from a splay alignment to a bend alignment, and a display panel control circuit that controls transmittance of the display panel by a liquid crystal driving voltage. In particular, the display panel has a voltage-transmittance characteristic that a minimum value and maximum value of the transmittance are obtained in a state where the liquid crystal driving voltage exceeds a transfer threshold level at which an energy of the splay alignment is balanced with an energy of the bend alignment, and the display panel control circuit is configured to vary the liquid crystal driving voltage in a range corresponding to the minimum and maximum values of transmittance.

摘要翻译： 液晶显示装置包括显示面板，其包括一对电极基板和液晶层，该液晶层保持在电极基板之间并且包含其分子预先从喷射取向转移到弯曲取向的液晶材料，并且 显示面板控制电路，其通过液晶驱动电压来控制显示面板的透射率。 特别地，显示面板具有在液晶驱动电压超过喷射取向的能量平衡的转印阈值水平的状态下获得透射率的最小值和最大值的电压透过率特性， 弯曲取向的能量和显示面板控制电路被配置为在与透射率的最小值和最大值对应的范围内改变液晶驱动电压。

公开(公告)号：US20060022923A1

公开(公告)日：2006-02-02

申请号：US11247714

申请日：2005-10-11

申请人： Yukio Tanaka

发明人： Yukio Tanaka

IPC分类号： G09G3/36

CPC分类号： G09G3/2092 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/0218

摘要： To provide a liquid crystal panel employing a circuit layout that makes it possible to obtain a small size liquid crystal panel when the area a source driver occupies is large. A liquid crystal display device of the present invention comprises: a pixel portion including m×n pixels (m and n are both natural numbers and satisfy the relation m

摘要翻译： 提供一种采用电路布局的液晶面板，当电源驱动器占据的面积大时，可以获得小尺寸液晶面板。 本发明的液晶显示装置包括：包括m×n个像素（m和n都是自然数并满足关系m