公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US07512924B2

公开(公告)日：2009-03-31

申请号：US11333618

申请日：2006-01-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

IPC分类号： G06F17/50

CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

公开(公告)号：US07125802B2

公开(公告)日：2006-10-24

申请号：US10696432

申请日：2003-10-29

申请人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

发明人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

IPC分类号： H01L21/306

CPC分类号： C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

公开(公告)号：US20050272260A1

公开(公告)日：2005-12-08

申请号：US10861149

申请日：2004-06-04

申请人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

发明人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

公开(公告)号：US20050236716A1

公开(公告)日：2005-10-27

申请号：US10829583

申请日：2004-04-22

申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

公开(公告)号：US20050153537A1

公开(公告)日：2005-07-14

申请号：US10753637

申请日：2004-01-08

申请人： Yi-Lung Cheng ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ying-Lung Wang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826

摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.

摘要翻译： 公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。 将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。 氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。 复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

公开(公告)号：US20050121751A1

公开(公告)日：2005-06-09

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

公开(公告)号：US20050106858A1

公开(公告)日：2005-05-19

申请号：US10716818

申请日：2003-11-19

申请人： Yi-Lung Cheng ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Ying-Lang Wang

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831

摘要： A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.

摘要翻译： 公开了一种用于减少半导体器件中的金属扩散的方法。 在衬底上形成第一金属部分之后，在第一金属部分上沉积硅碳氧化物（SiCNO）层。 在SiCNO层上沉积介电层，在SiCNO层和第二金属部分的介电层上产生开口以连接到第一金属部分，其中SiCNO层将第一金属部分的扩散减少到 电介质层。

公开(公告)号：US06802935B2

公开(公告)日：2004-10-12

申请号：US10103618

申请日：2002-03-21

申请人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B65G4907

CPC分类号： H01L21/67167 ,  C23C16/4405 ,  C23C16/54 ,  H01L21/67196 ,  Y10S414/135

摘要： A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

摘要翻译： 本文公开了包括多个处理室的半导体处理装置和方法，其中在多个处理室中的每个处理室内发生至少一个半导体处理操作。 此外，本文公开的装置和方法包括机器人机构，用于在完成相关联的半导体处理操作时在多个处理室中旋转每个处理室。 这样的机器人机构可以包括多个机器人。 具体地说，这样的多个机器人可以包括配置在相关转盘上的六个机器人。

公开(公告)号：US06584987B1

公开(公告)日：2003-07-01

申请号：US09808929

申请日：2001-03-16

申请人： Yi-Lung Cheng ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Yin-Lang Wang

发明人： Yi-Lung Cheng ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Yin-Lang Wang

IPC分类号： B08B704

CPC分类号： H01J37/32862 ,  B08B7/0035 ,  C23C16/4405 ,  Y10S438/905

摘要： A method for cleaning residual material from a chemical vapor deposition (CVD) apparatus in situ employing dry etching. There is first employed a high density plasma chemical vapor deposition (HDP-CVD) method to deposit layers of silicon oxide material upon substrates within a chemical vapor deposition reactor apparatus. After removal of substrates, the reactor chamber is closed off. The interior of the reactor is then filled with a gas and a plasma formed therewithin, to which oxygen is added and the reactor allowed to come to an increased temperature and bake for a period of time. The reactor power is then turned off and the reactor evacuated. There is then carried out a normal cleaning step within the reactor chamber employing a reactive gas such as NF3, with greater cleaning efficiency due to the increased temperature caused by the baking step.

摘要翻译： 一种从化学气相沉积（CVD）装置中原位采用干法蚀刻来清除残余物质的方法。 首先采用高密度等离子体化学气相沉积（HDP-CVD）方法在化学气相沉积反应器装置中的衬底上沉积氧化硅材料层。 在移除基板之后，关闭反应室。 然后将反应器的内部填充有在其中形成的气体和等离子体，向其中加入氧并使反应器升温并烘烤一段时间。 然后关闭反应堆功率，反应器排空。 然后，使用反应气体如NF3在反应器室内进行正常的清洗步骤，由于烘烤步骤引起的温度升高，清洗效率更高。