公开(公告)号：US20060125090A1

公开(公告)日：2006-06-15

申请号：US11338551

申请日：2006-01-24

申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/34

CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

公开(公告)号：US20050236716A1

公开(公告)日：2005-10-27

申请号：US10829583

申请日：2004-04-22

申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

公开(公告)号：US07420277B2

公开(公告)日：2008-09-02

申请号：US10801475

申请日：2004-03-16

申请人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

发明人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.

摘要翻译： 本公开提供了一种用于半导体器件中散热的方法和系统。 在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

公开(公告)号：US07512924B2

公开(公告)日：2009-03-31

申请号：US11333618

申请日：2006-01-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

IPC分类号： G06F17/50

CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

公开(公告)号：US20070166887A1

公开(公告)日：2007-07-19

申请号：US11333618

申请日：2006-01-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

IPC分类号： H01L21/82

CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

公开(公告)号：US20050205991A1

公开(公告)日：2005-09-22

申请号：US10801475

申请日：2004-03-16

申请人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

发明人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

IPC分类号： H01L21/3205 ,  H01L21/44 ,  H01L21/768 ,  H01L21/82 ,  H01L23/34 ,  H01L23/433 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04

CPC分类号： H01L23/528 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.

摘要翻译： 本公开提供了一种用于半导体器件中散热的方法和系统。 在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

公开(公告)号：US20070267737A1

公开(公告)日：2007-11-22

申请号：US11383922

申请日：2006-05-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng

IPC分类号： H01L23/15

CPC分类号： H01L23/3121 ,  H01L23/293 ,  H01L23/295 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged devices and methods of forming packaged devices are provided. At least one device is disposed on a substrate. The material layer encapsulates the device and covers at least a portion of the substrate, wherein the material layer comprises at least a first portion adjacent to the device and a second portion over the first portion. The second portion has a thermal conductivity higher than a thermal conductivity of the first portion.

摘要翻译： 提供了封装器件和形成封装器件的方法。 至少一个装置设置在基板上。 所述材料层封装所述装置并且覆盖所述基板的至少一部分，其中所述材料层包括至少邻近所述装置的第一部分和所述第一部分上的第二部分。 第二部分具有高于第一部分的热导率的导热率。

公开(公告)号：US20060076694A1

公开(公告)日：2006-04-13

申请号：US10962478

申请日：2004-10-13

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng

IPC分类号： H01L23/28

CPC分类号： H01L23/3135 ,  H01L23/3121 ,  H01L23/367 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device package has a concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency. An encapsulation body of polymer-based material encapsulates a semiconductor device and bonding wires, and a concavity structure is patterned on the encapsulation body by imprinting, laser drilling, photolithography, dry etching, die sawing, or other surface patterning technologies.

摘要翻译： 半导体器件封装具有含凹入的封装体，以防止器件分层并提高热传递效率。 基于聚合物的材料的封装体封装半导体器件和接合线，并且通过压印，激光钻孔，光刻，干法蚀刻，模切或其它表面图案化技术在封装体上图案化凹形结构。

公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US20050112859A1

公开(公告)日：2005-05-26

申请号：US10718881

申请日：2003-11-21

申请人： Yi-Lung Cheng ,  Shih-Chia Cheng

发明人： Yi-Lung Cheng ,  Shih-Chia Cheng

IPC分类号： H01L21/31 ,  H01L21/311 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of forming an opening in a stack of insulator layers featuring an underlying etch stop layer comprised of a tri-layer insulator composite, has been developed. The tri-layer insulator composite comprised of a bottom silicon rich, silicon oxide layer and a top silicon nitride layer, is first formed on a conductive region of a semiconductor substrate. After deposition of overlying insulator layers a photoresist shape is used as a etch mask to allow the desired contact or via hole shape to be defined in the overlying insulator layers via a first phase of an anisotropic dry etch procedure, with the first phase of the dry etching procedure terminating at the top surface of the silicon nitride layer. An over etch procedure used to insure complete removal of overlying insulator layer from the surface of the tri-layer insulator composite, is next performed as a second phase of the anisotropic dry etch procedure. The high etch rate ratio of insulator layer to silicon nitride allows the over etch cycle to be successfully accomplished without risk to underlying materials. A third phase of the anisotropic dry etch procedure selectively removes the silicon nitride layer and subsequently selectively removes the silicon rich, silicon oxide layer without damage to the now exposed conductive region, resulting in definition of the desired contact or via hole openings in the stack of insulator layers.

摘要翻译： 已经开发了在堆叠的绝缘体层中形成开口的方法，其特征在于由三层绝缘体复合材料构成的下面的蚀刻停止层。 首先在半导体衬底的导电区域上形成由富硅底层，氧化硅层和顶部氮化硅层组成的三层绝缘体复合体。 在沉积上覆绝缘体层之后，使用光致抗蚀剂形状作为蚀刻掩模，以允许通过各向异性干蚀刻程序的第一阶段在上覆绝缘体层中限定所需的接触或通孔形状，其中第一相干燥 蚀刻过程终止于氮化硅层的顶表面。 接下来，进行用于确保从三层绝缘体复合材料的表面完全去除上覆绝缘体层的过蚀刻程序作为各向异性干蚀刻工艺的第二阶段。 绝缘体层与氮化硅的高蚀刻速率比允许成功地实现过蚀刻循环，而不会对下面的材料造成风险。 各向异性干蚀刻过程的第三阶段选择性地去除氮化硅层，随后选择性地除去富含硅的氧化硅层，而不损害现在暴露的导电区域，导致定义了堆叠中的所需接触或通孔开口 绝缘体层。