公开(公告)号：US20050042819A1

公开(公告)日：2005-02-24

申请号：US10726434

申请日：2003-12-03

申请人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

发明人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10838 ,  H01L27/10841

摘要： A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

摘要翻译： 用于部分垂直单元的双角舍入处理。 在蚀刻基板之后进行第一个圆角化处理以形成用于器件隔离的浅沟槽。 在形成浅沟槽隔离（STI）并且在存储单元阵列区域中的有源区域处暴露基板的角部之后，进行第二个角圆化处理。

公开(公告)号：US20160023123A1

公开(公告)日：2016-01-28

申请号：US14743070

申请日：2015-06-18

申请人： Ming-Cheng Chang

发明人： Ming-Cheng Chang

IPC分类号： A63J5/02 ,  F22B1/28

CPC分类号： A63J5/025 ,  F22B1/282 ,  F22B27/165

摘要： An instantaneous heater for a smoke generator includes a heating rod having first and second sections. The second section is connected to a power supply system of a smoke generator. An outer tube is mounted around the heating rod. An end cap is sealing mounted to a first end of the outer tube and covers the first section of the heating rod. The outer periphery of the heating rod, the inner periphery of the outer tube, the end cap, and the connection cap together defines a heating passage intercommunicating with an outlet of the end cap. A connection cap is sealingly mounted around a second end of the outer tube. The connection cap includes a coupling hole intercommunicating with the heating passage. A guiding tube is mounted between the coupling hole of the connection cap and an oil tank of the smoke generator.

摘要翻译： 用于烟雾发生器的瞬时加热器包括具有第一和第二部分的加热棒。 第二部分连接到烟雾发生器的电源系统。 外管安装在加热棒周围。 端盖密封安装到外管的第一端并覆盖加热棒的第一部分。 加热棒的外围，外管的内周，端盖和连接帽一起限定了与端帽的出口相互连通的加热通道。 连接帽被密封地安装在外管的第二端周围。 连接帽包括与加热通道相通的联接孔。 引导管安装在连接帽的联接孔和烟雾发生器的油箱之间。

公开(公告)号：US20090090955A1

公开(公告)日：2009-04-09

申请号：US12057391

申请日：2008-03-28

申请人： Jer-Chyi Wang ,  Ming-Cheng Chang ,  Yi-Feng Chang ,  Wei-Ming Liao ,  Chien-Chang Huang

发明人： Jer-Chyi Wang ,  Ming-Cheng Chang ,  Yi-Feng Chang ,  Wei-Ming Liao ,  Chien-Chang Huang

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7851

摘要： A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density.

摘要翻译： 一种闪存装置，其特征在于，具备：一体地形成有突出部的基板，两个浮置栅极，控制栅极和电介质层。 两个浮动门设置在突出部分的两侧并分别覆盖突出部分的一部分。 控制门设置在突出部分的顶部并夹在两个浮动门之间。 介电层设置在两个浮动栅极和控制栅极之间。 因为FLASH装置的控制门设置在突出部分上，所以可以形成升高的通道。 此外，由于两个浮栅的位置，可以增加有效浮栅（FG）长度而不影响单元密度。

公开(公告)号：US20090020801A1

公开(公告)日：2009-01-22

申请号：US11951344

申请日：2007-12-06

申请人： Wei-Ming Liao ,  Ming-Cheng Chang ,  Jer-Chyi Wang

发明人： Wei-Ming Liao ,  Ming-Cheng Chang ,  Jer-Chyi Wang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7887 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P+ source/drain region next to the spacer, and an N+ pocket region encompassing the P+ source/drain region and covering the area directly under the floating gate.

摘要翻译： 闪存单元包括衬底上的控制栅极氧化层，控制栅极氧化层上的T形控制栅极，设置在T形控制栅极的两个凹入侧壁上的浮置栅极，控制栅极之间的绝缘层 浮置栅极和浮置栅极之间的电介质层，浮置栅极的侧壁上的间隔物，隔着间隔物的P +源极/漏极区域和包围P +源极/漏极区域的N +穴状区域，以及 覆盖浮动门下方的区域。

公开(公告)号：US20080283904A1

公开(公告)日：2008-11-20

申请号：US11828334

申请日：2007-07-25

申请人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

发明人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

IPC分类号： H01L29/792

CPC分类号： H01L29/7887 ,  H01L29/40114

摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate.

摘要翻译： 两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，堆叠在栅极氧化物层上的栅极。 电荷存储间隔堆叠设置在栅极的任一侧。 电荷存储间隔堆叠包括底部电荷存储层和上部间隔层。 绝缘层设置在电荷存储间隔堆叠和栅极之间。 衬底设置在底部电荷存储层下面。 源极/漏极区域设置在衬底内的底部电荷存储层的一侧。

公开(公告)号：US07408215B2

公开(公告)日：2008-08-05

申请号：US11696160

申请日：2007-04-03

申请人： Ming-Cheng Chang ,  Neng-Tai Shih

发明人： Ming-Cheng Chang ,  Neng-Tai Shih

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10841 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10876

摘要： A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.

摘要翻译： 硅衬底上的DRAM结构具有有源区，栅极导体，深沟槽电容器和垂直晶体管。 深沟槽电容器形成在有源区和栅极导体的交点处，并且每个深沟槽电容器电耦合到相应的垂直晶体管以形成存储单元。 晶体管包括栅极，栅极的侧面中的源极和栅极的另一侧面中的漏极漏极的深度不同于源极的深度。

公开(公告)号：USD542957S1

公开(公告)日：2007-05-15

申请号：US29211865

申请日：2004-08-23

申请人： Ming-Cheng Chang

设计人： Ming-Cheng Chang

公开(公告)号：US06969881B2

公开(公告)日：2005-11-29

申请号：US10640100

申请日：2003-08-13

申请人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

发明人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L27/10832 ,  H01L27/10838 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/945

摘要： A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

摘要翻译： 局部垂直存储单元及其制造方法。 提供一种半导体衬底，其中分别形成具有深沟槽电容器的两个深沟槽，并且深沟槽电容器低于半导体衬底的顶表面。 在深沟槽外部的半导体的一部分被去除以在其之间形成柱。 柱被离子注入以在柱角中形成作为S / D区域的离子掺杂区域。 栅极电介质层和导电层依次形成在柱上。 在导电层旁边的半导体衬底中形成隔离。 导电层被限定为形成第一栅极和第二栅极。

公开(公告)号：US06929996B2

公开(公告)日：2005-08-16

申请号：US10726434

申请日：2003-12-03

申请人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

发明人： Chung-Peng Hao ,  Yi-Nan Chen ,  Ming-Cheng Chang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10838 ,  H01L27/10841

摘要： A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

公开(公告)号：US20050110066A1

公开(公告)日：2005-05-26

申请号：US10718666

申请日：2003-11-24

申请人： Ming-Cheng Chang

发明人： Ming-Cheng Chang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10897

摘要： Disclosed is a deep trench structure for a semiconductor memory device. The deep trench in accordance with the present invention has a cross section communicating with two difference active areas, which are respectively connected to two adjacent bit lines of the semiconductor memory device.

摘要翻译： 公开了一种用于半导体存储器件的深沟槽结构。 根据本发明的深沟槽具有与两个差分有效区域通信的横截面，其两个分别连接到半导体存储器件的两个相邻位线。