公开(公告)号：US20090212793A1

公开(公告)日：2009-08-27

申请号：US12037687

申请日：2008-02-26

Applicant: Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

Inventor： Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

IPC: G01R31/305 ,  H01L23/58

CPC classification number: H01L22/14 ,  G01R31/2884 ,  G01R31/307 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Abstract translation: 用于在半导体器件处理期间检测缺陷的方法可以包括提供具有电隔离应用的具有半导体层的衬底，并且在其上形成测试电路，将电子电流感应束引导到测试电路; 测量测试电路中的第一和第二接触焊盘之间的电流; 确定电子束感应电流（EBIC）; 以及基于EBIC和对应于EBIC的电子束的位置来识别测试电路中的一个或多个缺陷位置。 测试电路可以包括并联连接的多个半导体器件，耦合到半导体器件的第一端子的第一接触焊盘以及耦合到与半导体器件相关联的衬底端子的至少第二接触焊盘。

公开(公告)号：US20080268589A1

公开(公告)日：2008-10-30

申请号：US11742254

申请日：2007-04-30

Applicant: David Gerald Farber ,  Toan Tran ,  Craig Henry Huffman ,  Brian K. Kirkpatrick

Inventor： David Gerald Farber ,  Toan Tran ,  Craig Henry Huffman ,  Brian K. Kirkpatrick

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/76232 ,  H01L21/823481

Abstract: The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a patterned pad oxide layer located on a semiconductor substrate. The wet etch thereby produces a divot on upper lateral edges of a insulator-filled trench in the semiconductor substrate. Forming the shallow trench isolation structure also includes forming a nitride post on a vertical wall of the divot. Forming the nitride post includes depositing a nitride layer on the insulator, and dry etching the nitride layer. The dry etch is selective towards the nitride located adjacent the vertical wall such that a portion of the nitride layer remains on the vertical wall subsequent to the dry etching.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括形成浅沟槽隔离结构，包括执行湿蚀刻工艺以去除位于半导体衬底上的图案化衬垫氧化物层。 因此，湿蚀刻在半导体衬底中的绝缘体填充沟槽的上侧边缘上产生凹陷。 形成浅沟槽隔离结构还包括在该凹陷的垂直壁上形成氮化物柱。 形成氮化物柱包括在绝缘体上沉积氮化物层，并干蚀刻氮化物层。 干蚀刻对位于垂直壁附近的氮化物是选择性的，使得在干蚀刻之后，氮化物层的一部分保留在垂直壁上。

公开(公告)号：US20060183533A1

公开(公告)日：2006-08-17

申请号：US11281258

申请日：2005-11-17

Applicant: Toan Tran ,  Ichiro Tsuchida

Inventor： Toan Tran ,  Ichiro Tsuchida

IPC: A63F13/00

CPC classification number: G07F17/34 ,  G07F17/3267

Abstract: A gaming machine arranged to display a symbol in each element of a matrix of elements; each column of elements of said matrix of elements comprising a portion of a simulated rotatable reel and wherein at an occurrence of a trigger event at end of play of a main game; (a) said main game is completed and any prize is awarded, (b) at least one feature game may be awarded wherein each said rotatable reel is caused to be spun and brought to rest to display elements of said matrix in a first stage; said first stage displaying symbols in elements of at least one said column and uniform imagery in elements of each remaining said column; said feature game then progressing to a further stage wherein elements with said uniform imagery are populated by symbols of said elements of said at least one column.

Abstract translation: 布置成在元素矩阵的每个元素中显示符号的游戏机; 所述元件矩阵的每列元素包括模拟可旋转卷轴的一部分，并且其中在主游戏结束时发生触发事件; （a）所述主游戏完成并且任何奖品被授予，（b）可以授予至少一个特征游戏，其中使每个所述可旋转卷轴被旋转并使其休息以在第一阶段中显示所述矩阵的元素; 所述第一阶段在每个剩余的所述列的元素中显示至少一个所述列的元素中的符号和均匀的图像; 所述特征游戏然后进行到另一阶段，其中具有所述统一图像的元素由所述至少一列的所述元素的符号填充。

公开(公告)号：US20060140729A1

公开(公告)日：2006-06-29

申请号：US11020823

申请日：2004-12-27

Applicant: Toan Tran

Inventor： Toan Tran

IPC: B23C5/00

CPC classification number: B23B29/04 ,  B23B2200/28 ,  Y10T407/1906 ,  Y10T407/22

Abstract: The outer diameter roughing in a CNC lathe turning process utilizes generally inserts with zero degree negative clearance angle (N−0 degree Negative) for economic purposes. The common roughing tool holder is using the diamond shape insert, the so called CN_or DN_insert. In a variation of these conventional tool holders only one corner (mostly 80/55 degree) of the insert is in cutting operation. The other corner (110/125 degree) could be reused in another tool holder.

Abstract translation: 数控车床车削加工中的外径粗加工通常采用零度负间隙角（N-0度负）的插入件，用于经济目的。 普通的粗加工刀架采用金刚石形刀片，即所谓的CN_or DN_insert。 在这些常规刀架的变型中，刀片的一个角（大部分为80/55度）处于切割操作。 另一个角（110/125度）可以重新用于另一个工具架。

公开(公告)号：US06687973B2

公开(公告)日：2004-02-10

申请号：US09997980

申请日：2001-11-30

Applicant: Melissa M. Hewson ,  Ricky A. Jackson ,  Abha Singh ,  Toan Tran ,  Howard L. Tigelaar

Inventor： Melissa M. Hewson ,  Ricky A. Jackson ,  Abha Singh ,  Toan Tran ,  Howard L. Tigelaar

IPC: H01S400

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  Y10T29/49002 ,  Y10T29/49107 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).

Abstract translation: 金属熔断器工艺，其在顶部互连（102）上方使用较薄（例如，6000）的氧化物（108）。 在探针焊盘（106）上去除氧化物（108）用于测试，但不在保险丝（104）上移除。 因为氧化物（108）在熔丝（104）的上角处较薄，所以氧化物（108）在激光脉冲（114）期间在熔丝（104）上裂开。 然后使用湿蚀刻来溶解暴露的熔丝（104）。

公开(公告)号：US07772867B2

公开(公告)日：2010-08-10

申请号：US12037687

申请日：2008-02-26

Applicant: Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

Inventor： Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

IPC: G01R31/02

CPC classification number: H01L22/14 ,  G01R31/2884 ,  G01R31/307 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Abstract translation: 用于在半导体器件处理期间检测缺陷的方法可以包括提供具有电隔离应用的具有半导体层的衬底，并且在其上形成测试电路，将电子电流感应束引导到测试电路; 测量测试电路中的第一和第二接触焊盘之间的电流; 确定电子束感应电流（EBIC）; 以及基于EBIC和对应于EBIC的电子束的位置来识别测试电路中的一个或多个缺陷位置。 测试电路可以包括并联连接的多个半导体器件，耦合到半导体器件的第一端子的第一接触焊盘以及耦合到与半导体器件相关联的衬底端子的至少第二接触焊盘。

公开(公告)号：US20090205036A1

公开(公告)日：2009-08-13

申请号：US12068636

申请日：2008-02-08

Applicant: Jonathan Slaton ,  Ryan B. Johnson ,  Toan Tran ,  David Reed ,  Abhilash Ravindran ,  George K. Tsantes

Inventor： Jonathan Slaton ,  Ryan B. Johnson ,  Toan Tran ,  David Reed ,  Abhilash Ravindran ,  George K. Tsantes

IPC: G06F7/04 ,  H04L9/32

CPC classification number: H04L63/08 ,  G06Q20/36 ,  G06Q40/025 ,  H04L63/0815 ,  H04L63/083 ,  H04L63/0838 ,  H04L2463/082 ,  H04W12/06 ,  H04W12/08

Abstract: A system for secure information storage and delivery includes a vault repository that includes a secure vault associated with a user, wherein the secure vault is associated with a service level including at least one of a data type or a data size limit associated with the secure vault, the secure vault being adapted to receive and at least one data entry and securely store the at least one data entry if the at least one of a size or a type of the at least one data entry is consistent with the service level. A mobile vault server coupled to the vault repository creates a mobile vault on a mobile device based on the secure vault and is capable of authenticating the mobile device based on user authentication information. The mobile vault server includes a mobile device handler that communicates with the mobile device. A synchronization utility determines whether the at least one data entry on the secure vault is transferable to or storable on the mobile vault based on at least one of the size or the type of the at least one data entry and transfers the at least one data entry from the secure vault to a corresponding data entry on the mobile vault if the at least one data entry on the secure vault is determined to be transferable to or storable on the mobile vault.

Abstract translation: 用于安全信息存储和传递的系统包括保管库存储库，其包括与用户相关联的安全保险库，其中所述安全保险库与包括与所述安全保险库相关联的数据类型或数据大小限度中的至少一个的服务级别相关联 如果所述至少一个数据条目的大小或类型中的至少一个与所述服务级别一致，则所述安全库适于接收和至少一个数据条目并且安全地存储所述至少一个数据条目。 耦合到保管库存储库的移动保管库服务器基于安全保管库在移动设备上创建移动保管库，并且能够基于用户认证信息来认证移动设备。 移动保管库服务器包括与移动设备通信的移动设备处理程序。 同步实用程序基于至少一个数据条目的大小或类型来确定安全保险库上的至少一个数据条目是否可转移到或可存储在移动存储库上，并且传送至少一个数据条目 如果所述安全保险库上的所述至少一个数据条目被确定为可转移到或可存储在所述移动存储库上，则从所述保护库到所述移动存储库上的相应数据条目。

公开(公告)号：US20090102501A1

公开(公告)日：2009-04-23

申请号：US11875185

申请日：2007-10-19

Applicant: Richard L. Guldi ,  Toan Tran ,  Deepak Ramappa ,  Steven A. Lytle

Inventor： Richard L. Guldi ,  Toan Tran ,  Deepak Ramappa ,  Steven A. Lytle

IPC: G01N23/225 ,  G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/307 ,  H01L22/14 ,  H01L22/34

Abstract: In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.

Abstract translation: 根据本发明，存在电子束检查系统，电子束可测试半导体测试结构和用于检测系统缺陷的方法，例如接触到栅极短路，蠕虫孔泄漏路径，孔打印问题和异常 稀疏孔和随机缺陷，例如在半导体处理期间由于位错和管道引起的电流泄漏路径。

公开(公告)号：US07345001B2

公开(公告)日：2008-03-18

申请号：US10875482

申请日：2004-06-24

Applicant: Hiroaki Niimi ,  Husam N. Alshareef ,  Rajesh Khamankar ,  Toan Tran

Inventor： Hiroaki Niimi ,  Husam N. Alshareef ,  Rajesh Khamankar ,  Toan Tran

IPC: H01L29/72

CPC classification number: H01L21/3115 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.

Abstract translation: 本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。 在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮 等离子体工艺（510）的氦与氮的比例为3:1或更高。

公开(公告)号：US20050285211A1

公开(公告)日：2005-12-29

申请号：US10875482

申请日：2004-06-24

Applicant: Hiroaki Niimi ,  Husam Alshareef ,  Rajesh Khamankar ,  Toan Tran

Inventor： Hiroaki Niimi ,  Husam Alshareef ,  Rajesh Khamankar ,  Toan Tran

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/76

CPC classification number: H01L21/3115 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.

Abstract translation: 本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。 在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮 等离子体工艺（510）的氦与氮的比例为3:1或更高。