公开(公告)号：US07807522B2

公开(公告)日：2010-10-05

申请号：US11700278

申请日：2007-01-31

Applicant: Husam Alshareef ,  Manfred Ramin ,  Michael F. Pas

Inventor： Husam Alshareef ,  Manfred Ramin ,  Michael F. Pas

IPC: H01L21/338

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.

Abstract translation: 提供了半导体器件和制造方法，其中为MOS晶体管提供金属晶体管栅极。 在栅极电介质上形成金属氮化物。 将兰花系列金属注入到栅极电介质上方的金属屏蔽层中。 蓝色金属包含在屏幕层中或屏幕金属层和栅极电介质之间的界面处。 该过程提供了栅电极功函数的调整，从而调谐所得PMOS或NMOS晶体管的阈值电压。

公开(公告)号：US20080050882A1

公开(公告)日：2008-02-28

申请号：US11931529

申请日：2007-10-31

Applicant: Malcolm Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam Alshareef

Inventor： Malcolm Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam Alshareef

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US07332433B2

公开(公告)日：2008-02-19

申请号：US11233356

申请日：2005-09-22

Applicant: Kisik Choi ,  Husam Alshareef ,  Prashant Majhi

Inventor： Kisik Choi ,  Husam Alshareef ,  Prashant Majhi

IPC: H01R24/00

CPC classification number: H01L21/823842

Abstract: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques may be used to define the gate stack.

Abstract translation: 提供了用于制造用于互补金属氧化物半导体（CMOS）器件的具有不同功函数的两个金属栅极叠层的方法。第一金属层可沉积在栅极电介质上，随后沉积第二金属层，其中第二金属层调制 第一金属层的功函数。 第二金属层并随后蚀刻，暴露第一金属层的一部分。 可以在蚀刻的第二金属层和暴露的第一金属层上沉积第三金属层，其中第三金属层可以调节暴露的第一金属层的功函数。 可以使用随后的制造技术来定义栅极堆叠。

公开(公告)号：US20070284676A1

公开(公告)日：2007-12-13

申请号：US11745918

申请日：2007-05-08

Applicant: Husam Alshareef ,  Mark Visokay ,  Antonio Rotondaro ,  Luigi Colombo

Inventor： Husam Alshareef ,  Mark Visokay ,  Antonio Rotondaro ,  Luigi Colombo

IPC: H01L31/00

CPC classification number: H01L21/321 ,  H01L21/28079 ,  H01L21/823835 ,  H01L21/823842

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.

Abstract translation: 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135） 第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

公开(公告)号：US20060183337A1

公开(公告)日：2006-08-17

申请号：US11343680

申请日：2006-01-31

Applicant: Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

Inventor： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

IPC: H01L21/302 ,  C23F1/00 ,  B44C1/22

CPC classification number: H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

公开(公告)号：US20060084229A1

公开(公告)日：2006-04-20

申请号：US11292883

申请日：2005-12-02

Applicant: Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

Inventor： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

IPC: H01L21/8234

CPC classification number: H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

公开(公告)号：US08304333B2

公开(公告)日：2012-11-06

申请号：US12886863

申请日：2010-09-21

Applicant: Manfred Ramin ,  Michael F. Pas ,  Husam Alshareef

Inventor： Manfred Ramin ,  Michael F. Pas ,  Husam Alshareef

IPC: H01L21/3205 ,  H01L21/8238

CPC classification number: H01L21/02321 ,  H01L21/02156 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/3144 ,  H01L21/823462 ,  H01L21/823857

Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.

Abstract translation: 一种制造半导体器件的方法包括在栅极电介质上形成栅电极。 通过在氮化硅氧化物层上形成镧系元素金属层，然后对扩散原子进行退火以形成镧系元素氧氮化硅层来形成栅极电介质。 可以在退火之前或之后沉积栅极电极层。 在一个实施例中，栅极电极层包括非镧系元素金属层，形成在非镧系元素金属层上的阻挡层和形成在阻挡层上的多晶硅层。 可以将铪原子任选地注入到氮化硅氧化物层中。

公开(公告)号：US20090104743A1

公开(公告)日：2009-04-23

申请号：US11860066

申请日：2007-09-24

Applicant: Husam Alshareef ,  Manuel Quevedo Lopez

Inventor： Husam Alshareef ,  Manuel Quevedo Lopez

IPC: H01L21/8238 ,  H01L21/3115

CPC classification number: H01L21/28238 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric-transistor substrate interface.

Abstract translation: 使用现有技术制造的金属氧化物半导体（MOS）晶体管可以利用栅极电介质上的氮化工艺来提高晶体管的可靠性。 目前的技术的氮化，其涉及将栅极电介质暴露于氮化源，在栅极电介质和晶体管衬底的界面处产生显着的氮浓度，这对晶体管性能产生不利影响。 本发明包括在氮化之前在栅极电介质上沉积牺牲层的过程，将牺牲层暴露于氮化源，在此期间氮原子通过牺牲层扩散到栅极电介质中，然后去除牺牲层而不降低 栅电介质。 与本发明相关的高k栅极电介质的工作已经证明了在栅极介电晶体管衬底界面处的氮浓度降低了20％。

公开(公告)号：US20070059874A1

公开(公告)日：2007-03-15

申请号：US11456054

申请日：2006-07-06

Applicant: Naim Moumen ,  Husam Alshareef ,  Joel Barnett ,  Muhammad Hussain ,  Hongfa Luan ,  Seung-Chul Song ,  Raj Jammy

Inventor： Naim Moumen ,  Husam Alshareef ,  Joel Barnett ,  Muhammad Hussain ,  Hongfa Luan ,  Seung-Chul Song ,  Raj Jammy

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.

Abstract translation: 提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。 诸如金属层，金属合金层或金属氮化物层的公共层可以沉积到栅极电介质上。 可以在有源区上沉积和图案化第一掩模层，暴露公共层的一部分。 可以在形成第一掩模层的公共层中沉积第一离子。 类似地，第二掩模层可以在另一个有源区和第一金属层上沉积和图案化，并且公共层的另一部分被暴露。 可以在公共层中沉积第二离子，形成第二掩模层。

公开(公告)号：US20050221564A1

公开(公告)日：2005-10-06

申请号：US11145674

申请日：2005-06-06

Applicant: Malcolm Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam Alshareef

Inventor： Malcolm Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam Alshareef

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28202 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.