公开(公告)号：US6104052A

公开(公告)日：2000-08-15

申请号：US273573

申请日：1999-03-22

申请人： Tohru Ozaki ,  Yusuke Kohyama

发明人： Tohru Ozaki ,  Yusuke Kohyama

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/72

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/91

摘要： In a DRAM adopting a self-aligned contact structure, an opening portion of predetermined size is formed in advance in an insulation film which surrounds an on-field gate electrode formed on an element isolating insulation film. The on-field gate electrode contacts a gate contact through the opening portion. A contact hole for the gate contact can thus be formed in self-alignment as can be the contact holes for a bit-line contact and an active contact. Consequently, the contact hole for the gate contact reaching the on-field gate can be formed simultaneously with the contact holes for the bit-line contact and active contact, thereby greatly reducing the number of manufacturing steps.

摘要翻译： 在采用自对准接触结构的DRAM中，预先形成围绕形成在元件隔离绝缘膜上的场上栅电极的绝缘膜中的预定尺寸的开口部分。 场电极电极通过开口部分接触栅极接触。 因此，用于栅极接触的接触孔可以自对准地形成，就像位线接触和有源触点的接触孔一样。 因此，到达栅极栅极的接触孔可以与用于位线接触和有源接触的接触孔同时形成，从而大大减少了制造步骤的数量。

公开(公告)号：US5977583A

公开(公告)日：1999-11-02

申请号：US684059

申请日：1996-07-19

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

摘要翻译： 在制造COB DRAM单元的方法中，在与栅电极自对准的源极和漏极上形成多晶硅插塞。 在多晶硅插塞上形成位线接触和存储电极接触，从而减小位线接触和存储电极接触的纵横比。 由于多晶硅插塞形成与栅极电极自对准，不会发生相邻元件区域的触点短路和源极和漏极的插头短路，从而导致高度的不对准保护。 此外，不需要独立的光刻工艺来形成多晶硅插塞，因此，制造步骤的数量减少。

公开(公告)号：US06979866B2

公开(公告)日：2005-12-27

申请号：US10653128

申请日：2003-09-03

申请人： Atsushi Azuma ,  Yusuke Kohyama ,  Kaori Umezawa

发明人： Atsushi Azuma ,  Yusuke Kohyama ,  Kaori Umezawa

IPC分类号： H01L29/41 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/322 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L23/52 ,  H01L27/08 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the SOI region of a semiconductor substrate, a BOX layer is formed underneath with backgate electrodes to control the threshold voltages of MOS transistors formed in the SOI region.

摘要翻译： 在半导体衬底的SOI区域中，在底栅电极的下方形成BOX层，以控制在SOI区域中形成的MOS晶体管的阈值电压。

公开(公告)号：US20050023696A1

公开(公告)日：2005-02-03

申请号：US10927079

申请日：2004-08-27

申请人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Hiroyuki Nitta ,  Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/3213 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108 ,  H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/32134 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

公开(公告)号：US06720606B1

公开(公告)日：2004-04-13

申请号：US09660390

申请日：2000-09-12

申请人： Akihiro Nitayama ,  Katsuhiko Hieda ,  Shigeru Ishibashi ,  Yusuke Kohyama

发明人： Akihiro Nitayama ,  Katsuhiko Hieda ,  Shigeru Ishibashi ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/945

摘要： A semiconductor memory device has a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitors having a trench extends through the first semiconductor region and the second semiconductor region, and is formed such that its top does not reach a top surface of the second semiconductor region, and the trench is formed therein with a conductive trench fill. A pair of gate electrodes is formed on the second semiconductor region, overlying the trench capacitor. A pair of insulating layers is formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers. The conductive layer has a leading end insulated from the second semiconductor region and reaching the interior of the second semiconductor region, and electrically connected to the conductive trench fill of the trench capacitor. A pair of third semiconductor regions of the first conduction type are formed in the second semiconductor region, and positioned opposite to each other with respect to the conductive layer. Each of the third semiconductor regions is directly in contact with the conductive layer, and constitutes either a source or a drain of transistors having one of the pair of gate electrodes, respectively. The pair of third semiconductor regions is formed substantially to a uniform depth.

摘要翻译： 半导体存储器件具有形成在第一半导体区域上的半导体衬底，形成在半导体衬底上的第一导电类型的第一半导体区域，与第一导电类型相反的第二导电类型的第二半导体区域。 具有沟槽的沟槽电容器延伸穿过第一半导体区域和第二半导体区域，并且形成为使得其顶部不到达第二半导体区域的顶表面，并且沟槽在其中形成有导电沟槽填充物。 在第二半导体区上形成一对栅电极，覆盖在沟槽电容器上。 形成一对绝缘层以覆盖该对栅电极中的每一个。 在一对绝缘层之间形成导电层，以与一对绝缘层中的每一个自对准。 导电层具有与第二半导体区域绝缘​​并到达第二半导体区域的内部的前端，并且电连接到沟槽电容器的导电沟槽填充物。 第一导电类型的一对第三半导体区域形成在第二半导体区域中，并且相对于导电层彼此相对定位。 第三半导体区域中的每一个直接与导电层接触，并且分别构成具有一对栅极电极之一的晶体管的源极或漏极。 一对第三半导体区域基本上形成为均匀的深度。

公开(公告)号：US06635933B2

公开(公告)日：2003-10-21

申请号：US09953306

申请日：2001-09-17

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L2976

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

公开(公告)号：US06506634B1

公开(公告)日：2003-01-14

申请号：US09589124

申请日：2000-06-08

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L2182

CPC分类号： G11C29/72 ,  G11C29/789

摘要： A semiconductor memory device comprises: a memory cell array including memory cells arranged in the form of a matrix; a redundant cell array including redundant cells arranged for relieving a defective memory cell of the memory cell array; a defective address memory circuit including first and second memory circuits using different programming methods for storing an address of the defective memory cell of the memory cell array; and a substitution control circuit for controlling the substitution of one of the redundant cells of the redundant cell array for the defective memory cell of the memory cell array on the basis of memory data of the defective address memory circuit. Thus, it is possible to provide a semiconductor memory device capable of reducing the area occupied by a defective address memory circuit and surely carrying out defect relief, and a method for producing the same.

摘要翻译： 半导体存储器件包括：存储单元阵列，其包括以矩阵形式布置的存储单元; 冗余单元阵列，包括冗余单元，其布置用于缓冲所述存储单元阵列的有缺陷的存储单元; 缺陷地址存储电路，包括使用不同编程方法的第一和第二存储器电路，用于存储存储单元阵列的缺陷存储单元的地址; 以及替代控制电路，用于基于缺陷地址存储电路的存储器数据来控制对存储单元阵列的缺陷存储单元的冗余单元阵列中的一个冗余单元的替换。 因此，可以提供能够减少由缺陷地址存储电路占据的面积并确保进行缺陷消除的半导体存储器件及其制造方法。

公开(公告)号：US06362042B1

公开(公告)日：2002-03-26

申请号：US09664773

申请日：2000-09-19

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device having a stacked type capacitor excellent in storage capacity, breakdown voltage and reliability. A storage node electrode (Ru) of the stacked-type capacitor is formed on a contact hole of the underlying insulating film by the steps of forming the side wall of the contact hole diagonally at a taper angle within the range of 90 to 110°, forming a storage node electrode on the inner wall surface of the contact hole, filling SOG in the contact hole, etching off the Ru film on the insulating film using SOG as a mask, and etching off the Ru film formed on the upper peripheral region of the inner wall in the depth direction of the contact hole. Thereafter, the dielectric film of the stacked-type capacitor formed of a (Ba, Sr) TiO3 thin film is formed on the Ru storage node electrode. In this manner, it is possible to obtain a stack-type capacitor having a drastically-improved step coverage and a high breakdown voltage. In addition, it is easy to reduce the distance between adjacent Ru storage node electrodes within a resolution limit of lithography, compared to the conventional method.

摘要翻译： 提供一种半导体器件和制造具有存储容量，击穿电压和可靠性优异的堆叠型电容器的半导体器件的方法。 层叠型电容器的存储节点电极（Ru）通过以下步骤形成在下面的绝缘膜的接触孔上：将接触孔的侧壁对角地形成在90°至110°的范围内的锥角， 在接触孔的内壁表面上形成存储节点电极，在接触孔中填充SOG，使用SOG作为掩模蚀刻绝缘膜上的Ru膜，并且蚀刻形成在上部周边区域上的Ru膜 接触孔深度方向的内壁。 此后，在Ru储存节点电极上形成由（Ba，Sr）TiO 3薄膜形成的层叠型电容器的电介质膜。 以这种方式，可以获得具有急剧改善的台阶覆盖和高击穿电压的堆叠型电容器。 此外，与常规方法相比，在光刻的分辨率极限内容易地减小相邻Ru存储节点电极之间的距离。

公开(公告)号：US06333538B1

公开(公告)日：2001-12-25

申请号：US09388937

申请日：1999-09-02

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

摘要翻译： 在制造COB DRAM单元的方法中，在与栅电极自对准的源极和漏极上形成多晶硅插塞。 在多晶硅插塞上形成位线接触和存储电极接触，从而减小位线接触和存储电极接触的纵横比。 由于多晶硅插塞形成与栅极电极自对准，不会发生相邻元件区域的触点短路和源极和漏极的插头短路，从而导致高度的不对准保护。 此外，不需要独立的光刻工艺来形成多晶硅插塞，因此，制造步骤的数量减少。

公开(公告)号：US06320260B1

公开(公告)日：2001-11-20

申请号：US08694194

申请日：1996-08-08

申请人： Yusuke Kohyama ,  Souichi Sugiura

发明人： Yusuke Kohyama ,  Souichi Sugiura

IPC分类号： H01L2348

CPC分类号： H01L27/10805 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysiliccon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

摘要翻译： 在层间绝缘膜中形成用于位线的第一接触孔，并且在接触孔的内表面和层间绝缘膜上形成多晶硅膜。 接着，使用抗蚀剂作为掩模对聚硅氧烷膜进行各向同性干法蚀刻，对层间绝缘膜进行RIE蚀刻，从而在外围电路区域的层间绝缘膜中形成第二接触孔。 然后，在第二接触孔的内表面和多晶硅膜上形成层压膜，并且第二接触孔填充有填充构件。 层压膜和多晶硅膜被图案化，从而在存储单元区域中形成位线。