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142 条记录 (耗时 0.051 秒)

    Knitted-in slide fastener
    12.
    发明授权
    Knitted-in slide fastener 失效
    针织拉链

    公开(公告)号：US07240521B2

    公开(公告)日：2007-07-10

    申请号：US11384902

    申请日：2006-03-20

    申请人： Yoshio Matsuda

    发明人： Yoshio Matsuda

    IPC分类号： D04B21/20

    CPC分类号： A44B19/343 ,  A44B19/56 ,  D04B21/16 ,  D10B2501/0631

    摘要： A knitted-in slide fastener in which a continuous fastener element row can be mounted stably in its dimensional meaning and firmly while breaking of a needle is prevented, so as to secure a smooth engagement of elements, wherein the continuous fastener element row is fixed and knitted-in by a fixing chain knitting yarn at the same time when a fastener tape is knitted, the fixing chain knitting yarn for the elements is knitted into plural wales of a fastener element attaching portion on one side edge of the fastener tape, warp knitting yarns to be knitted for reinforcement are entangled with a needle loop formed by a constituent yarn of at least one of wales in a foundation structure adjoining the plural wales through their needle loops but not entangled with a needle loop of the fixing chain knitting yarn through their needle loops.

    摘要翻译： 一种编织的拉链，其中防止连续的拉链牙列在其尺寸意义上稳定地被安装并且在破裂时牢固地被安装，以便确保连续的拉链牙排固定的元件的平滑接合， 在编织拉链带的同时通过固定链编织纱编织，用于元件的固定链编织纱被编织成拉链带的一个侧边缘上的拉链牙齿附着部分的多个纵行，经编 用于加强的针织纱线与通过其针环相邻的多个纵行的基础结构中的至少一个纵行的组成纱线形成的针环缠绕，但是没有与固定链编织纱线的针环缠结通过它们 针环。

    Knit-in slide fastener
    13.
    发明授权
    Knit-in slide fastener 失效

    公开(公告)号：US06651296B2

    公开(公告)日：2003-11-25

    申请号：US10155784

    申请日：2002-05-24

    申请人： Yoshio Matsuda

    发明人： Yoshio Matsuda

    IPC分类号： A44B1956

    CPC分类号： A44B19/343 ,  D04B21/16 ,  D10B2501/0631 ,  Y10T24/252 ,  Y10T24/2523 ,  Y10T24/2527 ,  Y10T24/2529

    摘要： There is provided a knit-in slide fastener in which a continuous fastener element row is knitted simultaneously with the knitting of a warp knitted fastener tape at a fastener element mounting portion on a longitudinal side edge portion of the fastener tape. Since a yarn composed of ordinary long fibers, or a textured yarn is employed as a fixing knitting yarn for the fastener element mounting portion, even if a sewing needle is pierced into the textured yarn, the fixing knitting yarn is never cut off because the sewing needle passes through a number of fibers which compose the textured yarn. Further, even when part of the fibers are cut off, no fraying occurs in the yarns, so that the fastener element row at the cut off portions does not separate from the fastener tape.

    Semiconductor memory device for simple cache system
    14.
    发明授权
    Semiconductor memory device for simple cache system 失效
    半导体存储器件，用于简单缓存系统

    公开(公告)号：US06404691B1

    公开(公告)日：2002-06-11

    申请号：US08472770

    申请日：1995-06-07

    申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC分类号： G11C700

    CPC分类号： G06F12/0893 ,  G11C7/1021

    摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

    摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

    Semiconductor memory device with redundancy circuit
    15.
    发明授权
    Semiconductor memory device with redundancy circuit 失效
    具有冗余电路的半导体存储器件

    公开(公告)号：US6075732A

    公开(公告)日：2000-06-13

    申请号：US334917

    申请日：1999-06-17

    申请人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

    发明人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

    IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

    CPC分类号： G11C29/806 ,  G11C29/781 ,  G11C8/10

    摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

    摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE） ），并且由行解码器组（4a，4b）选择有缺陷的行。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。

    Knit slide fastener with reinforced edge section for attachment of chain
    16.
    发明授权
    Knit slide fastener with reinforced edge section for attachment of chain 失效
    针织拉链带有加固边缘部分，用于连接链条

    公开(公告)号：US5685177A

    公开(公告)日：1997-11-11

    申请号：US649077

    申请日：1996-05-16

    申请人： Yoshio Matsuda ,  Hidenobu Kato ,  Yoshito Ikeguchi

    发明人： Yoshio Matsuda ,  Hidenobu Kato ,  Yoshito Ikeguchi

    IPC分类号： A44B19/56 ,  A44B19/34 ,  D04B23/05

    CPC分类号： A44B19/343 ,  D04B21/16 ,  D10B2501/0631

    摘要： In a knit slide fastener in which a continuous fastener element row is knitted in a fastener element attaching portion of each fastener tape simultaneously with the knitting of the fastener tape, a plurality of laid-in weft yarns are knitted in the warp-knit structure of the fastener element attaching portion so as to turn alternately in every course and to be interlaced with knit loops of a chain stitch extending along the outermost edge of the fastener element attaching portion, and the fastener element row is secured to the ground structure of the attaching portion by two binding chain stitches.

    摘要翻译： 在针织拉链中，连续的拉链牙排与拉链带的编织同时编织在每个拉链带的拉链牙固定部分中，多根纬纱以经编针织结构编织 所述紧固件元件安装部分在每个路线中交替地转动并且与沿所述拉链件附接部分的最外边缘延伸的链式线迹的编织圈交错，并且所述拉链件排固定到所述连接件的接地结构 部分通过两个绑定链式线迹。

    Semiconductor memory device with redundancy circuit
    17.
    发明授权
    Semiconductor memory device with redundancy circuit 失效
    具有冗余电路的半导体存储器件

    公开(公告)号：US5504713A

    公开(公告)日：1996-04-02

    申请号：US180166

    申请日：1994-01-11

    申请人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

    发明人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/806 ,  G11C29/781

    摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

    摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）和缺陷行中存在缺陷行时产生备用行解码器选择信号（＆amp; upbar＆S） 由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（＆amp; S＆amp; S）和块控制信号被激活。

    Semiconductor memory device for simple cache system
    18.
    发明授权
    Semiconductor memory device for simple cache system 失效
    半导体存储器件，用于简单缓存系统

    公开(公告)号：US5226147A

    公开(公告)日：1993-07-06

    申请号：US564657

    申请日：1990-08-09

    申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC分类号： G06F12/08 ,  G11C7/10

    CPC分类号： G06F12/0893 ,  G11C7/1021

    摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

    摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

    Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers
    19.
    发明授权
    Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers 失效
    包括交叉点和多个互连层的半导体存储器件的位线结构

    公开(公告)号：US5214601A

    公开(公告)日：1993-05-25

    申请号：US876690

    申请日：1992-04-28

    申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC分类号： G11C5/06 ,  G11C7/18

    CPC分类号： G11C5/063 ,  G11C7/18

    摘要： A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N (N being an integer), although advantages of the invention may be obtained with division of the bit lines into 3N, and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. In a preferred embodiment, the cross parts are provided in regions for forming restore circuits or sense amplifiers. In a further embodiment, a dummy word line for selecting dummy cells for providing a reference potential is selected according to the position of a selected word line.

    摘要翻译： 折叠位线结构的半导体存储器件包括每个位线对的至少一部分中的交叉部分，使得与相邻位线对的耦合电容值相对于成对的位线彼此相等。 优选地，各位线对被均等地划分为4N（N是整数），尽管可以通过将位线划分为3N来获得本发明的优点，并且在分割点处提供交叉部分，使得位线对 将相同分割点处的交叉部分布置在交替的位线对上。 在优选实施例中，交叉部分设置在用于形成恢复电路或感测放大器的区域中。 在另一实施例中，根据所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Data descrambling in semiconductor memory device
    20.
    发明授权
    Data descrambling in semiconductor memory device 失效
    半导体存储器件中的数据解扰

    公开(公告)号：US5136543A

    公开(公告)日：1992-08-04

    申请号：US741208

    申请日：1991-07-31

    申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

    发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1006

    摘要： A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with complementary data. A switching circuit is provided on each bit line pair. Each switching circuit, in response to a control signal according to an address signal, respectively couples the first and the second bit lines to the first and the second input/output lines, or inversely, respectively couples the first and the second bit lines to the second and the first input/output lines.

    摘要翻译： 半导体存储器件包括多个位线对和一个输入/输出线对。 每个位线对包括提供有互补数据的第一和第二位线，并且输入/输出线对包括提供有互补数据的第一和第二输入/输出线。 在每个位线对上提供开关电路。 每个开关电路响应于根据地址信号的控制信号分别将第一和第二位线耦合到第一和第二输入/输出线，或者相反地将第一和第二位线耦合到 第二个和第一个输入/输出线。