公开(公告)号：US08278700B2

公开(公告)日：2012-10-02

申请号：US13072211

申请日：2011-03-25

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US08214982B2

公开(公告)日：2012-07-10

申请号：US12360435

申请日：2009-01-27

申请人： Takashi Kobayashi

发明人： Takashi Kobayashi

IPC分类号： H04R17/10 ,  H01L41/047

CPC分类号： H03H9/1021 ,  H03H3/02 ,  H03H9/0547 ,  H03H9/21 ,  Y10T29/42 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49574

摘要： To carry out frequency adjustment easily, accurately and efficiently without being influenced by a size of a piezoelectric vibrating piece and achieve low cost formation and promotion of maintenance performance, there is provided a method of fabricating a piezoelectric vibrating piece which is a method of fabricating a piezoelectric vibrating piece having a piezoelectric vibrating plate 11, a pair of exciting electrodes 12, 13, and a pair of mount electrodes 15, 16 by utilizing a wafer S, the method including an outer shape forming step of forming a frame portion S1 at a wafer and forming a plurality of piezoelectric plates at the frame portion to be connected thereto by way of a connecting portion 11a, an electrode forming step of forming pairs of exciting electrodes and pairs of mount electrodes respectively at the plurality of piezoelectric plates and forming a common electrode S2 respectively electrically connected to a plurality of the pairs of mount electrodes 15 on one side by way of the connecting portion, a frequency adjusting step of adjusting a frequency of the piezoelectric plate by applying a drive voltage between the common electrode and the mount electrode 16 on other side, and a cutting step of fragmenting the plurality of piezoelectric plates.

摘要翻译： 为了容易地，准确而有效地进行频率调整而不受压电振动片的尺寸的影响，并且实现低成本形成和提高维护性能，提供了一种制造压电振动片的方法，该方法是制造 具有压电振动板11的压电振动片，利用晶片S的一对激励电极12,13和一对安装电极15,16，该方法包括：外形形成步骤，以在 晶片，并通过连接部分11a在框架部分形成多个压电板，电极形成步骤分别在多个压电板上形成一对激励电极和一对安装电极，并形成共同的 电极S2分别电连接到一对侧的多对安装电极15上 连接部分的ay;频率调节步骤，通过在公共电极和另一侧的安装电极16之间施加驱动电压来调节压电板的频率，以及分割多个压电板的切割步骤。

公开(公告)号：US08174229B2

公开(公告)日：2012-05-08

申请号：US12420358

申请日：2009-04-08

申请人： Masashi Fujita ,  Shuichi Nakagawa ,  Takashi Kobayashi

发明人： Masashi Fujita ,  Shuichi Nakagawa ,  Takashi Kobayashi

IPC分类号： B64C17/06

CPC分类号： H01J37/20 ,  H01J2237/20228 ,  H01J2237/20285 ,  H01J2237/20292

摘要： The present invention provides a stage apparatus capable of reducing a positioning time without increasing a positional deviation. A positioning control method of a sample stage apparatus includes: a high-speed movement step of moving a table to a high-speed movement target position at a first movement speed; a positional deviation correcting step of moving the table to a low-speed positioning step start position at a second movement speed that is lower than the first movement speed; a low-speed positioning step of moving the table to a target position at a third movement speed that is lower than the second movement speed. After the low-speed positioning step is completed, a rod connected to a motor returns to its original position to separate a pin of the rod side from a concave portion of the table side.

摘要翻译： 本发明提供一种能够在不增加位置偏差的情况下减少定位时间的舞台装置。 采样台装置的定位控制方法包括：以第一移动速度将桌子移动到高速移动目标位置的高速移动步骤; 位置偏差校正步骤，以低于第一移动速度的第二移动速度将桌子移动到低速定位步骤开始位置; 低速定位步骤，以低于第二移动速度的第三移动速度将桌子移动到目标位置。 在低速定位步骤完成之后，连接到电动机的杆返回到其原始位置，以将杆侧的销与台侧的凹部分开。

公开(公告)号：US08173932B2

公开(公告)日：2012-05-08

申请号：US12178263

申请日：2008-07-23

申请人： Takashi Kobayashi ,  Akihiro Nemoto ,  Hiroaki Yamagishi ,  Katsuyuki Nakajima

发明人： Takashi Kobayashi ,  Akihiro Nemoto ,  Hiroaki Yamagishi ,  Katsuyuki Nakajima

IPC分类号： B23K26/38

CPC分类号： B23K26/18 ,  B23K26/389

摘要： A perforation method and an perforation apparatus in which a hollow member of a fuel injection nozzle is filled with a filler such as a zirconia ball, and a laser light is applied to the hollow member to form an injection hole while vibrating the zirconia ball using an ultrasonic vibrator. After the injection hole is formed, the laser light is introduced through the injection hole to the inside of the fuel injection nozzle, and thereby is applied to the vibrated zirconia ball.

摘要翻译： 一种穿孔方法和穿孔装置，其中燃料喷嘴的中空构件填充有诸如氧化锆球的填料，并且激光被施加到中空构件以形成喷射孔，同时使用 超声波振动器。 在形成注射孔之后，将激光通过注射孔引入燃料喷嘴的内部，由此施加到振动的氧化锆球上。

公开(公告)号：US08106395B2

公开(公告)日：2012-01-31

申请号：US12113923

申请日：2008-05-01

申请人： Shuntaro Machida ,  Takashi Kobayashi

发明人： Shuntaro Machida ,  Takashi Kobayashi

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L22/32 ,  B81C99/0045 ,  G01R31/2884 ,  H01L21/78 ,  H01L2224/05554

摘要： A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a plurality of test areas sectioned by chip areas is prepared. Next, pads to be electrically connected to the device are formed at corresponding positions on the respective plurality of test areas. Subsequently, the respective test areas are tested by a same probe card via the plurality of pads.

摘要翻译： 提供了即使对于大面积芯片也能够通过普通的测试装置进行探针测试的半导体器件的制造技术。 制备包括通过半导体工艺在器件区域上形成并包括由芯片区域划分的多个测试区域的器件的芯片。 接下来，在相应的多个测试区域上的相应位置处形成要与该器件电连接的焊盘。 随后，通过多个焊盘通过相同的探针卡测试各个测试区域。

公开(公告)号：US20110284817A1

公开(公告)日：2011-11-24

申请号：US13109985

申请日：2011-05-17

申请人： Yoshitaka SASAGO ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

发明人： Yoshitaka SASAGO ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Takashi Kobayashi

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/2481 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472

摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

摘要翻译： 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶粒边界。

公开(公告)号：US07972973B2

公开(公告)日：2011-07-05

申请号：US12443137

申请日：2007-09-28

申请人： Takashi Kobayashi ,  Toshihiko Shinozawa ,  Yoshiro Abe ,  Junichi Kitagawa

发明人： Takashi Kobayashi ,  Toshihiko Shinozawa ,  Yoshiro Abe ,  Junichi Kitagawa

IPC分类号： H01L21/31 ,  H01L21/469 ,  C23C14/00 ,  C23C8/36

CPC分类号： H01L21/76232 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28211 ,  H01L21/28247 ,  H01L21/3143 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/4236 ,  H01L29/66795

摘要： The present invention provides a method for forming a silicon oxide film, with a substantially uniform film thickness and without being so influenced by dense sites and scattered sites in a pattern provided on an object to be processed, while keeping advantageous points of a plasma oxidation process performed under a lower-pressure and lower-oxygen-concentration condition. In this method, plasma of a processing gas is applied to a surface of the object having a concavo-convex pattern, in a processing chamber of a plasma processing apparatus, so as to oxidize silicon on the surface of the object, thereby forming the silicon oxide film. The plasma is generated under the condition that a ratio of oxygen in the processing gas is within a range of 0.1% to 10% and pressure is within a range of 0.133 Pa to 133.3 Pa. This plasma oxidation process is performed, with a plate, having a plurality of through-holes formed therein, being provided between a region for generating the plasma in the processing chamber and the object to be processed.

摘要翻译： 本发明提供一种形成氧化硅膜的方法，其具有基本上均匀的膜厚度，并且不受等离子体氧化工艺的优点的保证，在受加工物体上设置的图案中的致密部位和散射部位的影响 在低压和低氧浓度条件下进行。 在该方法中，在等离子体处理装置的处理室中，将处理气体的等离子体施加到具有凹凸图案的物体的表面，以氧化物体表面上的硅，从而形成硅 氧化膜。 在处理气体中的氧的比例在0.1〜10％的范围内且压力在0.133Pa〜133.3Pa的范围内的条件下产生等离子体，用等离子体氧化法， 具有形成在其中的多个通孔，设置在处理室中用于产生等离子体的区域和待处理物体之间。

公开(公告)号：US07969067B2

公开(公告)日：2011-06-28

申请号：US12161962

申请日：2006-11-14

申请人： Takanori Aono ,  Tatsuya Nagata ,  Katsunori Asafusa ,  Takashi Kobayashi ,  Naoya Kanda

发明人： Takanori Aono ,  Tatsuya Nagata ,  Katsunori Asafusa ,  Takashi Kobayashi ,  Naoya Kanda

IPC分类号： H01L41/08

CPC分类号： G10K11/002 ,  A61B8/00

摘要： There is provided an ultrasound probe including a first substrate having a silicon substrate and an ultrasound transmit-receive element, an acoustic lens disposed over an upper surface of the first substrate, and a damping layer disposed under the first substrate, in which a second substrate is disposed between a lower surface of the first substrate and an upper surface of the damping layer, and the second substrate is made of a material having approximately the same linear expansion coefficient and acoustic impedance as the silicon substrate of the first substrate. With this structure, it is possible to provide the ultrasound probe which can prevent damage to the silicon substrate due to temperature change and has excellent transmission/reception performance and structure reliability while reducing noise by reflected waves in transmission and reception.

摘要翻译： 提供一种超声波探头，其包括具有硅衬底和超声波发射接收元件的第一衬底，设置在第一衬底的上表面上的声透镜，以及设置在第一衬底下方的阻尼层，其中第二衬底 设置在第一基板的下表面和阻尼层的上表面之间，第二基板由具有与第一基板的硅基板大致相同的线膨胀系数和声阻抗的材料制成。 利用这种结构，可以提供能够防止由于温度变化而损坏硅基板的超声波探头，并且在发送和接收中减少反射波的噪声的同时具有优异的发送/接收性能和结构可靠性。

公开(公告)号：US07939879B2

公开(公告)日：2011-05-10

申请号：US11896800

申请日：2007-09-06

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US07910495B2

公开(公告)日：2011-03-22

申请号：US12443589

申请日：2007-09-27

申请人： Toshihiko Shiozawa ,  Yoshiro Kabe ,  Takashi Kobayashi ,  Hikaru Adachi ,  Junichi Kitagawa ,  Nobuhiko Yamamoto

发明人： Toshihiko Shiozawa ,  Yoshiro Kabe ,  Takashi Kobayashi ,  Hikaru Adachi ,  Junichi Kitagawa ,  Nobuhiko Yamamoto

IPC分类号： H01L21/469

CPC分类号： H01L21/76229 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662 ,  H01L21/7621

摘要： A plasma oxidizing method includes a step of placing an object to be processed and having a surface containing silicon on a susceptor disposed in a processing vessel of a plasma processing apparatus, a step of producing a plasma from a processing gas containing oxygen in the processing vessel, a step of supplying high-frequency electric power to the susceptor and applying a high-frequency bias to the object to be processed when the plasma is produced, and a step of forming a silicon oxide film by oxidizing silicon in the surface of the object to be processed by the plasma.

摘要翻译： 等离子体氧化方法包括将待处理物体放置在等离子体处理装置的处理容器中的基座上的步骤，在处理容器内从含有氧的处理气体生成等离子体的步骤 向基座提供高频电力的步骤，在制造等离子体时向待处理物体施加高频偏压的步骤，以及通过在物体的表面氧化硅来形成氧化硅膜的步骤 由等离子体处理。